mirror of
https://github.com/espressif/esp-idf.git
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change(esp_rom): optimize target-specific header files layout in components/esp_rom
This commit is contained in:
Xiaoyu Liu
46
components/esp_rom/esp32c3/include/esp32c3/rom/aes.h
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46
components/esp_rom/esp32c3/include/esp32c3/rom/aes.h
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@@ -0,0 +1,46 @@
|
||||
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_AES_H_
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#define _ROM_AES_H_
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AES_BLOCK_SIZE 16
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enum AES_TYPE {
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AES_ENC,
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AES_DEC,
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};
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enum AES_BITS {
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AES128,
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AES192,
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AES256
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};
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void ets_aes_enable(void);
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void ets_aes_disable(void);
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int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits);
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int ets_aes_setkey_enc(const void *key, enum AES_BITS bits);
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int ets_aes_setkey_dec(const void *key, enum AES_BITS bits);
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void ets_aes_block(const void *input, void *output);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_AES_H_ */
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@@ -0,0 +1,17 @@
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/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void));
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#ifdef __cplusplus
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}
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#endif
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35
components/esp_rom/esp32c3/include/esp32c3/rom/bigint.h
Normal file
35
components/esp_rom/esp32c3/include/esp32c3/rom/bigint.h
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@@ -0,0 +1,35 @@
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/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_BIGINT_H_
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#define _ROM_BIGINT_H_
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ets_bigint_enable(void);
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void ets_bigint_disable(void);
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int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words);
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int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words);
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int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words);
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void ets_bigint_wait_finish(void);
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int ets_bigint_getz(uint32_t *z, uint32_t len_words);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_BIGINT_H_ */
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750
components/esp_rom/esp32c3/include/esp32c3/rom/cache.h
Normal file
750
components/esp_rom/esp32c3/include/esp32c3/rom/cache.h
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@@ -0,0 +1,750 @@
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_CACHE_H_
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#define _ROM_CACHE_H_
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#include <stdint.h>
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup cache_apis, cache operation related apis
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* @brief cache apis
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*/
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/** @addtogroup cache_apis
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* @{
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*/
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#define MIN_ICACHE_SIZE 16384
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#define MAX_ICACHE_SIZE 16384
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#define MIN_ICACHE_WAYS 8
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#define MAX_ICACHE_WAYS 8
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#define MAX_CACHE_WAYS 8
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#define MIN_CACHE_LINE_SIZE 32
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#define TAG_SIZE 4
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#define MIN_ICACHE_BANK_NUM 1
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#define MAX_ICACHE_BANK_NUM 1
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#define CACHE_MEMORY_BANK_NUM 1
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#define CACHE_MEMORY_IBANK_SIZE 0x4000
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#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
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#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
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#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
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#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
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typedef enum {
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CACHE_DCACHE = 0,
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CACHE_ICACHE0 = 1,
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CACHE_ICACHE1 = 2,
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} cache_t;
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typedef enum {
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CACHE_MEMORY_INVALID = 0,
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CACHE_MEMORY_IBANK0 = BIT(0),
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CACHE_MEMORY_IBANK1 = BIT(1),
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CACHE_MEMORY_IBANK2 = BIT(2),
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CACHE_MEMORY_IBANK3 = BIT(3),
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CACHE_MEMORY_DBANK0 = BIT(0),
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CACHE_MEMORY_DBANK1 = BIT(1),
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CACHE_MEMORY_DBANK2 = BIT(2),
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CACHE_MEMORY_DBANK3 = BIT(3),
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} cache_array_t;
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#define ICACHE_SIZE_16KB CACHE_SIZE_HALF
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#define ICACHE_SIZE_32KB CACHE_SIZE_FULL
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#define DCACHE_SIZE_32KB CACHE_SIZE_HALF
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#define DCACHE_SIZE_64KB CACHE_SIZE_FULL
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typedef enum {
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CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
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CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
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} cache_size_t;
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typedef enum {
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CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */
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CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */
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} cache_ways_t;
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typedef enum {
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CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */
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CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */
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CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */
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} cache_line_size_t;
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typedef enum {
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CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */
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CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */
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} cache_autoload_order_t;
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#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
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typedef enum {
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CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */
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CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */
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CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */
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} cache_autoload_trigger_t;
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typedef enum {
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CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
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CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
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} cache_freeze_mode_t;
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struct cache_mode {
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uint32_t cache_size; /*!< cache size in byte */
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uint16_t cache_line_size; /*!< cache line size in byte */
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uint8_t cache_ways; /*!< cache ways, always 4 */
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uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */
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};
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struct icache_tag_item {
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uint32_t valid:1; /*!< the tag item is valid or not */
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uint32_t lock:1; /*!< the cache line is locked or not */
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uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
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uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
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uint32_t reserved:14;
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};
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struct autoload_config {
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uint8_t order; /*!< autoload step is positive or negative */
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uint8_t trigger; /*!< autoload trigger */
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uint8_t ena0; /*!< autoload region0 enable */
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uint8_t ena1; /*!< autoload region1 enable */
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uint32_t addr0; /*!< autoload region0 start address */
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uint32_t size0; /*!< autoload region0 size */
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uint32_t addr1; /*!< autoload region1 start address */
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uint32_t size1; /*!< autoload region1 size */
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};
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struct tag_group_info {
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struct cache_mode mode; /*!< cache and cache mode */
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uint32_t filter_addr; /*!< the address that used to generate the struct */
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uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */
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uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */
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uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */
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};
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struct lock_config {
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uint32_t addr; /*!< manual lock address*/
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uint16_t size; /*!< manual lock size*/
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uint16_t group; /*!< manual lock group, 0 or 1*/
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};
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struct cache_internal_stub_table {
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uint32_t (* icache_line_size)(void);
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uint32_t (* icache_addr)(uint32_t addr);
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uint32_t (* dcache_addr)(uint32_t addr);
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void (* invalidate_icache_items)(uint32_t addr, uint32_t items);
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void (* lock_icache_items)(uint32_t addr, uint32_t items);
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void (* unlock_icache_items)(uint32_t addr, uint32_t items);
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uint32_t (* suspend_icache_autoload)(void);
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void (* resume_icache_autoload)(uint32_t autoload);
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void (* freeze_icache_enable)(cache_freeze_mode_t mode);
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void (* freeze_icache_disable)(void);
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int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t));
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};
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/* Defined in the interface file, default value is rom_default_cache_internal_table */
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extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
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typedef void (* cache_op_start)(void);
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typedef void (* cache_op_end)(void);
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typedef struct {
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cache_op_start start;
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cache_op_end end;
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} cache_op_cb_t;
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/* Defined in the interface file, default value is NULL */
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extern const cache_op_cb_t* rom_cache_op_cb;
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#define ESP_ROM_ERR_INVALID_ARG 1
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#define MMU_SET_ADDR_ALIGNED_ERROR 2
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#define MMU_SET_PASE_SIZE_ERROR 3
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#define MMU_SET_VADDR_OUT_RANGE 4
|
||||
|
||||
#define CACHE_OP_ICACHE_Y 1
|
||||
#define CACHE_OP_ICACHE_N 0
|
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|
||||
/**
|
||||
* @brief Initialise cache mmu, mark all entries as invalid.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_MMU_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Set ICache mmu mapping.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
|
||||
* esp32c3, external memory is always flash
|
||||
*
|
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* @param uint32_t vaddr : virtual address in CPU address space.
|
||||
* Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t paddr : physical address in external memory.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
|
||||
*
|
||||
* @param uint32_t num : pages to be set.
|
||||
*
|
||||
* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
|
||||
*
|
||||
* @return uint32_t: error status
|
||||
* 0 : mmu set success
|
||||
* 2 : vaddr or paddr is not aligned
|
||||
* 3 : psize error
|
||||
* 4 : vaddr is out of range
|
||||
*/
|
||||
int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
|
||||
/**
|
||||
* @brief Set DCache mmu mapping.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
|
||||
* esp32c3, external memory is always flash
|
||||
*
|
||||
* @param uint32_t vaddr : virtual address in CPU address space.
|
||||
* Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t paddr : physical address in external memory.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
|
||||
*
|
||||
* @param uint32_t num : pages to be set.
|
||||
|
||||
* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
|
||||
*
|
||||
* @return uint32_t: error status
|
||||
* 0 : mmu set success
|
||||
* 2 : vaddr or paddr is not aligned
|
||||
* 3 : psize error
|
||||
* 4 : vaddr is out of range
|
||||
*/
|
||||
int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
|
||||
/**
|
||||
* @brief Count the pages in the bus room address which map to Flash.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t bus : the bus to count with.
|
||||
*
|
||||
* @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count.
|
||||
*
|
||||
* return uint32_t : the number of pages which map to Flash.
|
||||
*/
|
||||
uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
|
||||
|
||||
/**
|
||||
* @brief allocate memory to used by ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0
|
||||
*
|
||||
* return none
|
||||
*/
|
||||
void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low);
|
||||
|
||||
/**
|
||||
* @brief Get cache mode of ICache or DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
|
||||
*
|
||||
* return none
|
||||
*/
|
||||
void Cache_Get_Mode(struct cache_mode * mode);
|
||||
|
||||
/**
|
||||
* @brief Init Cache for ROM boot, including resetting the Icache, initializing Owner, MMU, setting ICache mode, Enabling ICache, unmasking bus.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ROM_Boot_Cache_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Init mmu owner register to make i/d cache use half mmu entries.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Owner_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Invalidate the cache items for ICache.
|
||||
* Operation will be done CACHE_LINE_SIZE aligned.
|
||||
* If the region is not in ICache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr: start address to invalidate
|
||||
*
|
||||
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items);
|
||||
|
||||
/**
|
||||
* @brief Invalidate the Cache items in the region from ICache or DCache.
|
||||
* If the region is not in Cache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : invalidated region start address.
|
||||
*
|
||||
* @param uint32_t size : invalidated region size.
|
||||
*
|
||||
* @return 0 for success
|
||||
* 1 for invalid argument
|
||||
*/
|
||||
int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/**
|
||||
* @brief Invalidate all cache items in ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Invalidate_ICache_All(void);
|
||||
|
||||
/**
|
||||
* @brief Mask all buses through ICache and DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Mask_All(void);
|
||||
|
||||
/**
|
||||
* @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : 0 for ICache not auto preload before suspend.
|
||||
*/
|
||||
uint32_t Cache_Suspend_ICache_Autoload(void);
|
||||
|
||||
/**
|
||||
* @brief Resume ICache auto preload operation after some ICache operations.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : 0 for ICache not auto preload before suspend.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void Cache_Resume_ICache_Autoload(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Start an ICache manual preload, will suspend auto preload of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : start address of the preload region.
|
||||
*
|
||||
* @param uint32_t size : size of the preload region, should not exceed the size of ICache.
|
||||
*
|
||||
* @param uint32_t order : the preload order, 0 for positive, other for negative
|
||||
*
|
||||
* @return uint32_t : 0 for ICache not auto preload before manual preload.
|
||||
*/
|
||||
uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order);
|
||||
|
||||
/**
|
||||
* @brief Return if the ICache manual preload done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : 0 for ICache manual preload not done.
|
||||
*/
|
||||
uint32_t Cache_ICache_Preload_Done(void);
|
||||
|
||||
/**
|
||||
* @brief End the ICache manual preload to resume auto preload of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_End_ICache_Preload(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Config autoload parameters of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct autoload_config * config : autoload parameters.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Config_ICache_Autoload(const struct autoload_config * config);
|
||||
|
||||
/**
|
||||
* @brief Enable auto preload for ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Enable_ICache_Autoload(void);
|
||||
|
||||
/**
|
||||
* @brief Disable auto preload for ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Disable_ICache_Autoload(void);
|
||||
|
||||
/**
|
||||
* @brief Config a group of prelock parameters of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct lock_config * config : a group of lock parameters.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
|
||||
void Cache_Enable_ICache_PreLock(const struct lock_config *config);
|
||||
|
||||
/**
|
||||
* @brief Disable a group of prelock parameters for ICache.
|
||||
* However, the locked data will not be released.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint16_t group : 0 for group0, 1 for group1.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Disable_ICache_PreLock(uint16_t group);
|
||||
|
||||
/**
|
||||
* @brief Lock the cache items for ICache.
|
||||
* Operation will be done CACHE_LINE_SIZE aligned.
|
||||
* If the region is not in ICache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr: start address to lock
|
||||
*
|
||||
* @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items);
|
||||
|
||||
/**
|
||||
* @brief Unlock the cache items for ICache.
|
||||
* Operation will be done CACHE_LINE_SIZE aligned.
|
||||
* If the region is not in ICache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr: start address to unlock
|
||||
*
|
||||
* @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items);
|
||||
|
||||
/**
|
||||
* @brief Lock the cache items in tag memory for ICache or DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : start address of lock region.
|
||||
*
|
||||
* @param uint32_t size : size of lock region.
|
||||
*
|
||||
* @return 0 for success
|
||||
* 1 for invalid argument
|
||||
*/
|
||||
int Cache_Lock_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/**
|
||||
* @brief Unlock the cache items in tag memory for ICache or DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : start address of unlock region.
|
||||
*
|
||||
* @param uint32_t size : size of unlock region.
|
||||
*
|
||||
* @return 0 for success
|
||||
* 1 for invalid argument
|
||||
*/
|
||||
int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/**
|
||||
* @brief Disable ICache access for the cpu.
|
||||
* This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @return uint32_t : auto preload enabled before
|
||||
*/
|
||||
uint32_t Cache_Disable_ICache(void);
|
||||
|
||||
/**
|
||||
* @brief Enable ICache access for the cpu.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : ICache will preload then.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Enable_ICache(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Suspend ICache access for the cpu.
|
||||
* The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
|
||||
* Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : auto preload enabled before
|
||||
*/
|
||||
uint32_t Cache_Suspend_ICache(void);
|
||||
|
||||
/**
|
||||
* @brief Resume ICache access for the cpu.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : ICache will preload then.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Resume_ICache(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Get ICache cache line size
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t: 16, 32, 64 Byte
|
||||
*/
|
||||
uint32_t Cache_Get_ICache_Line_Size(void);
|
||||
|
||||
/**
|
||||
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Set_Default_Mode(void);
|
||||
|
||||
/**
|
||||
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Enable_Defalut_ICache_Mode(void);
|
||||
|
||||
/**
|
||||
* @brief Enable freeze for ICache.
|
||||
* Any miss request will be rejected, including cpu miss and preload/autoload miss.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Disable freeze for ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Freeze_ICache_Disable(void);
|
||||
|
||||
/**
|
||||
* @brief Travel tag memory to run a call back function.
|
||||
* ICache and DCache are suspend when doing this.
|
||||
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the cache to check and the cache mode.
|
||||
*
|
||||
* @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
|
||||
* 0 for do not filter, all cache lines will be returned.
|
||||
*
|
||||
* @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
|
||||
|
||||
/**
|
||||
* @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
|
||||
*
|
||||
* @param uint32_t tag : the tag part of a tag item, 12-14 bits.
|
||||
*
|
||||
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
|
||||
*
|
||||
* @return uint32_t : the virtual address.
|
||||
*/
|
||||
uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
|
||||
|
||||
/**
|
||||
* @brief Get cache memory block base address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t icache : 0 for dcache, other for icache.
|
||||
*
|
||||
* @param uint32_t bank_no : 0 ~ 3 bank.
|
||||
*
|
||||
* @return uint32_t : the cache memory block base address, 0 if the block not used.
|
||||
*/
|
||||
uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
|
||||
|
||||
/**
|
||||
* @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
|
||||
*
|
||||
* @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line.
|
||||
*
|
||||
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
|
||||
*
|
||||
* @return uint32_t : the virtual address.
|
||||
*/
|
||||
uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset);
|
||||
|
||||
/**
|
||||
* @brief Get the cache memory value by DRAM address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address.
|
||||
*
|
||||
* @return uint32_t : the word value of the address.
|
||||
*/
|
||||
uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the cache MMU IROM end address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return uint32_t : the word value of the address.
|
||||
*/
|
||||
uint32_t Cache_Get_IROM_MMU_End(void);
|
||||
|
||||
/**
|
||||
* @brief Get the cache MMU DROM end address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return uint32_t : the word value of the address.
|
||||
*/
|
||||
uint32_t Cache_Get_DROM_MMU_End(void);
|
||||
|
||||
/**
|
||||
* @brief Configure cache MMU page size according to instruction and rodata size
|
||||
*
|
||||
* @param irom_size The instruction cache MMU page size
|
||||
* @param drom_size The rodata data cache MMU page size
|
||||
*/
|
||||
void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
|
||||
|
||||
/**
|
||||
* @brief Lock the permission control section configuration. After lock, any
|
||||
* configuration modification will be bypass. Digital reset will clear the lock!
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Pms_Lock(int ibus);
|
||||
|
||||
/**
|
||||
* @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ibus_boundary0_addr : vaddress for split line0
|
||||
*
|
||||
* @param uint32_t ibus_boundary1_addr : vaddress for split line1
|
||||
*
|
||||
* @param uint32_t ibus_boundary2_addr : vaddress for split line2
|
||||
*
|
||||
* @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
|
||||
*/
|
||||
int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr);
|
||||
|
||||
/**
|
||||
* @brief Set three ibus pms attribute, which will determine pms in different section and world.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ibus_pms_sct2_attr : attr for section2
|
||||
*
|
||||
* @param uint32_t ibus_pms_sct1_attr : attr for section1
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr);
|
||||
|
||||
/**
|
||||
* @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t dbus_boundary0_addr : vaddress for split line0
|
||||
*
|
||||
* @param uint32_t dbus_boundary1_addr : vaddress for split line1
|
||||
*
|
||||
* @param uint32_t dbus_boundary2_addr : vaddress for split line2
|
||||
*
|
||||
* @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
|
||||
*/
|
||||
int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr);
|
||||
|
||||
/**
|
||||
* @brief Set three dbus pms attribute, which will determine pms in different section and world.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t dbus_pms_sct2_attr : attr for section2
|
||||
*
|
||||
* @param uint32_t dbus_pms_sct1_attr : attr for section1
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_CACHE_H_ */
|
||||
119
components/esp_rom/esp32c3/include/esp32c3/rom/crc.h
Normal file
119
components/esp_rom/esp32c3/include/esp32c3/rom/crc.h
Normal file
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ROM_CRC_H
|
||||
#define ROM_CRC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup crc_apis, uart configuration and communication related apis
|
||||
* @brief crc apis
|
||||
*/
|
||||
|
||||
/** @addtogroup crc_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Standard CRC8/16/32 algorithms. */
|
||||
// CRC-8 x8+x2+x1+1 0x07
|
||||
// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
|
||||
// CRC32:
|
||||
//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
|
||||
//If your buf is not continuous, you can use the first result to be the second parameter.
|
||||
|
||||
/**
|
||||
* @brief Crc32 value that is in little endian.
|
||||
*
|
||||
* @param uint32_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Crc32 value that is in big endian.
|
||||
*
|
||||
* @param uint32_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Crc16 value that is in little endian.
|
||||
*
|
||||
* @param uint16_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Crc16 value that is in big endian.
|
||||
*
|
||||
* @param uint16_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Crc8 value that is in little endian.
|
||||
*
|
||||
* @param uint8_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Crc8 value that is in big endian.
|
||||
*
|
||||
* @param uint32_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,142 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define ETS_DS_MAX_BITS 3072
|
||||
|
||||
#define ETS_DS_IV_LEN 16
|
||||
|
||||
/* Length of parameter 'C' stored in flash (not including IV)
|
||||
|
||||
Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8)
|
||||
|
||||
Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware
|
||||
*/
|
||||
#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8)
|
||||
|
||||
/* Encrypted ETS data. Recommended to store in flash in this format.
|
||||
*/
|
||||
typedef struct {
|
||||
/* RSA LENGTH register parameters
|
||||
* (number of words in RSA key & operands, minus one).
|
||||
*
|
||||
*
|
||||
* This value must match the length field encrypted and stored in 'c',
|
||||
* or invalid results will be returned. (The DS peripheral will
|
||||
* always use the value in 'c', not this value, so an attacker can't
|
||||
* alter the DS peripheral results this way, it will just truncate or
|
||||
* extend the message and the resulting signature in software.)
|
||||
*/
|
||||
unsigned rsa_length;
|
||||
|
||||
/* IV value used to encrypt 'c' */
|
||||
uint8_t iv[ETS_DS_IV_LEN];
|
||||
|
||||
/* Encrypted Digital Signature parameters. Result of AES-CBC encryption
|
||||
of plaintext values. Includes an encrypted message digest.
|
||||
*/
|
||||
uint8_t c[ETS_DS_C_LEN];
|
||||
} ets_ds_data_t;
|
||||
|
||||
typedef enum {
|
||||
ETS_DS_OK,
|
||||
ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */
|
||||
ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */
|
||||
ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */
|
||||
ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */
|
||||
} ets_ds_result_t;
|
||||
|
||||
void ets_ds_enable(void);
|
||||
|
||||
void ets_ds_disable(void);
|
||||
|
||||
|
||||
/*
|
||||
* @brief Start signing a message (or padded message digest) using the Digital Signature peripheral
|
||||
*
|
||||
* - @param message Pointer to message (or padded digest) containing the message to sign. Should be
|
||||
* (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data
|
||||
* in flash.
|
||||
*
|
||||
* Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling
|
||||
* this function, and is responsible for calling ets_ds_finish_sign() and then
|
||||
* ets_hmac_invalidate_downstream() afterwards.
|
||||
*
|
||||
* @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid,
|
||||
* EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly.
|
||||
*/
|
||||
ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data);
|
||||
|
||||
|
||||
/*
|
||||
* @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign()
|
||||
*
|
||||
* A result of false indicates that a call to ets_ds_finish_sign() will not block.
|
||||
*
|
||||
* Only valid if ets_ds_enable() has been called.
|
||||
*/
|
||||
bool ets_ds_is_busy(void);
|
||||
|
||||
|
||||
/* @brief Finish signing a message using the Digital Signature peripheral
|
||||
*
|
||||
* Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until
|
||||
* peripheral is no longer busy.
|
||||
*
|
||||
* - @param signature Pointer to buffer to contain the signature. Should be
|
||||
* (data->rsa_length + 1)*4 bytes long.
|
||||
* - @param data Should match the 'data' parameter passed to ets_ds_start_sign()
|
||||
*
|
||||
* @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid,
|
||||
* ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the
|
||||
* encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a
|
||||
* digest is produced anyhow.)
|
||||
*/
|
||||
ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data);
|
||||
|
||||
|
||||
/* Plaintext parameters used by Digital Signature.
|
||||
|
||||
Not used for signing with DS peripheral, but can be encrypted
|
||||
in-device by calling ets_ds_encrypt_params()
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Y[ETS_DS_MAX_BITS / 32];
|
||||
uint32_t M[ETS_DS_MAX_BITS / 32];
|
||||
uint32_t Rb[ETS_DS_MAX_BITS / 32];
|
||||
uint32_t M_prime;
|
||||
uint32_t length;
|
||||
} ets_ds_p_data_t;
|
||||
|
||||
typedef enum {
|
||||
ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */
|
||||
ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */
|
||||
} ets_ds_key_t;
|
||||
|
||||
/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral
|
||||
*
|
||||
* @param data Output buffer to store encrypted data, suitable for later use generating signatures.
|
||||
* @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
|
||||
* @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored.
|
||||
* @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased.
|
||||
* @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral)
|
||||
*
|
||||
* @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters.
|
||||
*/
|
||||
ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
346
components/esp_rom/esp32c3/include/esp32c3/rom/efuse.h
Normal file
346
components/esp_rom/esp32c3/include/esp32c3/rom/efuse.h
Normal file
@@ -0,0 +1,346 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_EFUSE_H_
|
||||
#define _ROM_EFUSE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/** \defgroup efuse_APIs efuse APIs
|
||||
* @brief ESP32 efuse read/write APIs
|
||||
* @attention
|
||||
*
|
||||
*/
|
||||
|
||||
/** @addtogroup efuse_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
ETS_EFUSE_KEY_PURPOSE_USER = 0,
|
||||
ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
|
||||
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
|
||||
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
|
||||
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
|
||||
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
|
||||
ETS_EFUSE_KEY_PURPOSE_MAX,
|
||||
} ets_efuse_purpose_t;
|
||||
|
||||
typedef enum {
|
||||
ETS_EFUSE_BLOCK0 = 0,
|
||||
ETS_EFUSE_MAC_SPI_SYS_0 = 1,
|
||||
ETS_EFUSE_BLOCK_SYS_DATA = 2,
|
||||
ETS_EFUSE_BLOCK_USR_DATA = 3,
|
||||
ETS_EFUSE_BLOCK_KEY0 = 4,
|
||||
ETS_EFUSE_BLOCK_KEY1 = 5,
|
||||
ETS_EFUSE_BLOCK_KEY2 = 6,
|
||||
ETS_EFUSE_BLOCK_KEY3 = 7,
|
||||
ETS_EFUSE_BLOCK_KEY4 = 8,
|
||||
ETS_EFUSE_BLOCK_KEY5 = 9,
|
||||
ETS_EFUSE_BLOCK_KEY6 = 10,
|
||||
ETS_EFUSE_BLOCK_MAX,
|
||||
} ets_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief set timing according the apb clock, so no read error or write error happens.
|
||||
*
|
||||
* @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M.
|
||||
*
|
||||
* @return : 0 if success, others if clock not accepted
|
||||
*/
|
||||
int ets_efuse_set_timing(uint32_t clock);
|
||||
|
||||
/**
|
||||
* @brief Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return : 0 if success, others if apb clock is not accepted
|
||||
*/
|
||||
int ets_efuse_read(void);
|
||||
|
||||
/**
|
||||
* @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
|
||||
*
|
||||
* @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
|
||||
*
|
||||
* @return : 0 if success, others if apb clock is not accepted
|
||||
*/
|
||||
int ets_efuse_program(ets_efuse_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Set all Efuse program registers to zero.
|
||||
*
|
||||
* Call this before writing new data to the program registers.
|
||||
*/
|
||||
void ets_efuse_clear_program_registers(void);
|
||||
|
||||
/**
|
||||
* @brief Program a block of key data to an efuse block
|
||||
*
|
||||
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
|
||||
* @param purpose Purpose to set for this key. Purpose must be already unset.
|
||||
* @param data Pointer to data to write.
|
||||
* @param data_len Length of data to write.
|
||||
*
|
||||
* @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
|
||||
*/
|
||||
int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
|
||||
|
||||
|
||||
/* @brief Return the address of a particular efuse block's first read register
|
||||
*
|
||||
* @param block Index of efuse block to look up
|
||||
*
|
||||
* @return 0 if block is invalid, otherwise a numeric read register address
|
||||
* of the first word in the block.
|
||||
*/
|
||||
uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Return the current purpose set for an efuse key block
|
||||
*
|
||||
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
|
||||
*/
|
||||
ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
|
||||
|
||||
/**
|
||||
* @brief Find a key block with the particular purpose set
|
||||
*
|
||||
* @param purpose Purpose to search for.
|
||||
* @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
|
||||
* @return true if found, false if not found. If false, value at key_block pointer is unchanged.
|
||||
*/
|
||||
bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
|
||||
|
||||
/**
|
||||
* Return true if the key block is unused, false otherwise.
|
||||
*
|
||||
* An unused key block is all zero content, not read or write protected,
|
||||
* and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
|
||||
*
|
||||
* @param key_block key block to check.
|
||||
*
|
||||
* @return true if key block is unused, false if key block or used
|
||||
* or the specified block index is not a key block.
|
||||
*/
|
||||
bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Search for an unused key block and return the first one found.
|
||||
*
|
||||
* See @ref ets_efuse_key_block_unused for a description of an unused key block.
|
||||
*
|
||||
* @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
|
||||
*/
|
||||
ets_efuse_block_t ets_efuse_find_unused_key_block(void);
|
||||
|
||||
/**
|
||||
* @brief Return the number of unused efuse key blocks (0-6)
|
||||
*/
|
||||
unsigned ets_efuse_count_unused_key_blocks(void);
|
||||
|
||||
/**
|
||||
* @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
|
||||
*
|
||||
* @param data Pointer to data buffer (length 32 bytes)
|
||||
* @param rs_values Pointer to write encoded data to (length 12 bytes)
|
||||
*/
|
||||
void ets_efuse_rs_calculate(const void *data, void *rs_values);
|
||||
|
||||
/**
|
||||
* @brief Read spi flash pads configuration from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0 for default SPI pins.
|
||||
* - 1 for default HSPI pins.
|
||||
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
|
||||
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
|
||||
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
|
||||
*/
|
||||
uint32_t ets_efuse_get_spiconfig(void);
|
||||
|
||||
/**
|
||||
* @brief Read spi flash wp pad from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0x3f for invalid.
|
||||
* - 0~46 is valid.
|
||||
*/
|
||||
uint32_t ets_efuse_get_wp_pad(void);
|
||||
|
||||
/**
|
||||
* @brief Read if download mode disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable download mode.
|
||||
* - false for efuse doesn't disable download mode.
|
||||
*/
|
||||
bool ets_efuse_download_modes_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if legacy spi flash boot mode disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable legacy spi flash boot mode.
|
||||
* - false for efuse doesn't disable legacy spi flash boot mode.
|
||||
*/
|
||||
bool ets_efuse_legacy_spi_boot_mode_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if uart print control value from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0 for uart force print.
|
||||
* - 1 for uart print when GPIO8 is low when digital reset.
|
||||
* 2 for uart print when GPIO8 is high when digital reset.
|
||||
* 3 for uart force silent
|
||||
*/
|
||||
uint32_t ets_efuse_get_uart_print_control(void);
|
||||
|
||||
/**
|
||||
* @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 1 for efuse disable USB-Serial-JTAG print during rom boot.
|
||||
* - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot.
|
||||
*/
|
||||
uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if usb download mode disabled from Efuse
|
||||
*
|
||||
* (Also returns true if security download mode is enabled, as this mode
|
||||
* disables USB download.)
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable usb download mode.
|
||||
* - false for efuse doesn't disable usb download mode.
|
||||
*/
|
||||
bool ets_efuse_usb_download_mode_disabled(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read if usb module disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable usb module.
|
||||
* - false for efuse doesn't disable usb module.
|
||||
*/
|
||||
bool ets_efuse_usb_module_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if security download modes enabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse enable security download mode.
|
||||
* - false for efuse doesn't enable security download mode.
|
||||
*/
|
||||
bool ets_efuse_security_download_modes_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if secure boot is enabled in EFuse
|
||||
*/
|
||||
bool ets_efuse_secure_boot_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if secure boot aggressive revoke is enabled in EFuse
|
||||
*/
|
||||
bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse
|
||||
*/
|
||||
bool ets_efuse_cache_encryption_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU
|
||||
*/
|
||||
bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if EFuse indicates to send a flash resume command.
|
||||
*/
|
||||
bool ets_efuse_force_send_resume(void);
|
||||
|
||||
/**
|
||||
* @brief return the time in us ROM boot need wait flash to power on from Efuse
|
||||
*
|
||||
* @return
|
||||
* - uint32_t the time in us.
|
||||
*/
|
||||
uint32_t ets_efuse_get_flash_delay_us(void);
|
||||
|
||||
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
|
||||
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
|
||||
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
|
||||
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
|
||||
|
||||
/**
|
||||
* @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
|
||||
* the JTAG_CTRL registers.
|
||||
*
|
||||
* Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
|
||||
*
|
||||
* Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
|
||||
*
|
||||
* @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
|
||||
* @param key_block Index of a key block containing the source for this key.
|
||||
*
|
||||
* @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
|
||||
*/
|
||||
int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
|
||||
|
||||
/**
|
||||
* @brief A crc8 algorithm used for MAC addresses in efuse
|
||||
*
|
||||
* @param unsigned char const *p : Pointer to original data.
|
||||
*
|
||||
* @param unsigned int len : Data length in byte.
|
||||
*
|
||||
* @return unsigned char: Crc value.
|
||||
*/
|
||||
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_EFUSE_H_ */
|
||||
46
components/esp_rom/esp32c3/include/esp32c3/rom/esp_flash.h
Normal file
46
components/esp_rom/esp32c3/include/esp32c3/rom/esp_flash.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function
|
||||
just adds ROM-specific parts
|
||||
*/
|
||||
|
||||
struct spi_flash_chip_t;
|
||||
typedef struct esp_flash_t esp_flash_t;
|
||||
|
||||
/* Structure to wrap "global" data used by esp_flash in ROM */
|
||||
typedef struct {
|
||||
/* Default SPI flash chip, ie main chip attached to the MCU
|
||||
This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL
|
||||
*/
|
||||
esp_flash_t *default_chip;
|
||||
|
||||
/* Global API OS notification start/end/chip_check functions
|
||||
|
||||
These are used by ROM if no other host functions are configured.
|
||||
*/
|
||||
struct {
|
||||
esp_err_t (*start)(esp_flash_t *chip);
|
||||
esp_err_t (*end)(esp_flash_t *chip, esp_err_t err);
|
||||
esp_err_t (*chip_check)(esp_flash_t **inout_chip);
|
||||
} api_funcs;
|
||||
} esp_flash_rom_global_data_t;
|
||||
|
||||
/** Access a pointer to the global data used by the ROM spi_flash driver
|
||||
*/
|
||||
esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
455
components/esp_rom/esp32c3/include/esp32c3/rom/ets_sys.h
Normal file
455
components/esp_rom/esp32c3/include/esp32c3/rom/ets_sys.h
Normal file
@@ -0,0 +1,455 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_ETS_SYS_H_
|
||||
#define _ROM_ETS_SYS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup ets_sys_apis, ets system related apis
|
||||
* @brief ets system apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_sys_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* NOTE
|
||||
* Many functions in this header files can't be run in FreeRTOS.
|
||||
* Please see the comment of the Functions.
|
||||
* There are also some functions that doesn't work on FreeRTOS
|
||||
* without listed in the header, such as:
|
||||
* xtos functions start with "_xtos_" in ld file.
|
||||
*
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
/** \defgroup ets_apis, Espressif Task Scheduler related apis
|
||||
* @brief ets apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
ETS_OK = 0, /**< return successful in ets*/
|
||||
ETS_FAILED = 1, /**< return failed in ets*/
|
||||
ETS_PENDING = 2,
|
||||
ETS_BUSY = 3,
|
||||
ETS_CANCEL = 4,
|
||||
} ETS_STATUS;
|
||||
|
||||
typedef ETS_STATUS ets_status_t;
|
||||
|
||||
typedef uint32_t ETSSignal;
|
||||
typedef uint32_t ETSParam;
|
||||
|
||||
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
|
||||
|
||||
struct ETSEventTag {
|
||||
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
|
||||
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
|
||||
};
|
||||
|
||||
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/
|
||||
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_boot_apis, Boot routing related apis
|
||||
* @brief ets boot apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern const char *const exc_cause_table[40]; ///**< exception cause that defined by the core.*/
|
||||
|
||||
/**
|
||||
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
|
||||
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
|
||||
*
|
||||
* @param uint32_t start : the PRO Entry code address value in uint32_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_set_user_start(uint32_t start);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
|
||||
* @brief ets printf apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_printf_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
|
||||
* Can not print float point data format, or longlong data format.
|
||||
* So we maybe only use this in ROM.
|
||||
*
|
||||
* @param const char *fmt : See printf.
|
||||
*
|
||||
* @param ... : See printf.
|
||||
*
|
||||
* @return int : the length printed to the output device.
|
||||
*/
|
||||
int ets_printf(const char *fmt, ...);
|
||||
|
||||
/**
|
||||
* @brief Get the uart channel of ets_printf(uart_tx_one_char).
|
||||
*
|
||||
* @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
|
||||
*/
|
||||
uint8_t ets_get_printf_channel(void);
|
||||
|
||||
/**
|
||||
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
|
||||
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
|
||||
*
|
||||
* @param void (*)(char) p: Output function to install.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_putc1(void (*p)(char c));
|
||||
|
||||
/**
|
||||
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
|
||||
* To install putc2, which is defaulted installed as NULL.
|
||||
*
|
||||
* @param void (*)(char) p: Output function to install.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_putc2(void (*p)(char c));
|
||||
|
||||
/**
|
||||
* @brief Install putc1 as ets_write_char_uart.
|
||||
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_uart_printf(void);
|
||||
|
||||
#define ETS_PRINTF(...) ets_printf(...)
|
||||
|
||||
#define ETS_ASSERT(v) do { \
|
||||
if (!(v)) { \
|
||||
ets_printf("%s %u \n", __FILE__, __LINE__); \
|
||||
while (1) {}; \
|
||||
} \
|
||||
} while (0);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
|
||||
* @brief ets timer apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_timer_apis
|
||||
* @{
|
||||
*/
|
||||
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
|
||||
|
||||
typedef struct _ETSTIMER_ {
|
||||
struct _ETSTIMER_ *timer_next; /**< timer linker*/
|
||||
uint32_t timer_expire; /**< abstract time when timer expire*/
|
||||
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
|
||||
ETSTimerFunc *timer_func; /**< timer handler*/
|
||||
void *timer_arg; /**< timer handler argument*/
|
||||
} ETSTimer;
|
||||
|
||||
/**
|
||||
* @brief Init ets timer, this timer range is 640 us to 429496 ms
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_init(void);
|
||||
|
||||
/**
|
||||
* @brief In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_deinit(void);
|
||||
|
||||
/**
|
||||
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
|
||||
*
|
||||
* @param bool repeat : Timer is periodic repeated.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
|
||||
|
||||
/**
|
||||
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
|
||||
*
|
||||
* @param bool repeat : Timer is periodic repeated.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
|
||||
|
||||
/**
|
||||
* @brief Disarm an ets timer.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_disarm(ETSTimer *timer);
|
||||
|
||||
/**
|
||||
* @brief Set timer callback and argument.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param ETSTimerFunc *pfunction : Timer callback.
|
||||
*
|
||||
* @param void *parg : Timer callback argument.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
|
||||
|
||||
/**
|
||||
* @brief Unset timer callback and argument to NULL.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_done(ETSTimer *ptimer);
|
||||
|
||||
/**
|
||||
* @brief CPU do while loop for some time.
|
||||
* In FreeRTOS task, please call FreeRTOS apis.
|
||||
*
|
||||
* @param uint32_t us : Delay time in us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_delay_us(uint32_t us);
|
||||
|
||||
/**
|
||||
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
|
||||
* Call this function when CPU frequency is changed.
|
||||
*
|
||||
* @param uint32_t ticks_per_us : CPU ticks per us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_update_cpu_frequency(uint32_t ticks_per_us);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the real CPU ticks per us to the ets.
|
||||
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : CPU ticks per us record in ets.
|
||||
*/
|
||||
uint32_t ets_get_cpu_frequency(void);
|
||||
|
||||
/**
|
||||
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : if stored in efuse(not 0)
|
||||
* clock = ets_efuse_get_xtal_freq() * 1000000;
|
||||
* else if analog_8M in efuse
|
||||
* clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock();
|
||||
* else clock = 40M.
|
||||
*/
|
||||
uint32_t ets_get_xtal_freq(void);
|
||||
|
||||
/**
|
||||
* @brief Get the apb divior by xtal frequency.
|
||||
* When any types of reset happen, the default value is 2.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : 1 or 2.
|
||||
*/
|
||||
uint32_t ets_get_xtal_div(void);
|
||||
|
||||
/**
|
||||
* @brief Get apb_freq value, If value not stored in RTC_STORE5, than store.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
|
||||
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
|
||||
* else store ets_get_detected_xtal_freq() in.
|
||||
*/
|
||||
uint32_t ets_get_apb_freq(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_intr_apis, ets interrupt configure related apis
|
||||
* @brief ets intr apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_intr_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
|
||||
|
||||
/**
|
||||
* @brief Attach a interrupt handler to a CPU interrupt number.
|
||||
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param int i : CPU interrupt number.
|
||||
*
|
||||
* @param ets_isr_t func : Interrupt handler.
|
||||
*
|
||||
* @param void *arg : argument of the handler.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_attach(int i, ets_isr_t func, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Mask the interrupts which show in mask bits.
|
||||
* This function equals to _xtos_ints_off(mask).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_mask(uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Unmask the interrupts which show in mask bits.
|
||||
* This function equals to _xtos_ints_on(mask).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_unmask(uint32_t unmask);
|
||||
|
||||
/**
|
||||
* @brief Lock the interrupt to level 2.
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_intr_lock(void);
|
||||
|
||||
/**
|
||||
* @brief Unlock the interrupt to level 0.
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_intr_unlock(void);
|
||||
|
||||
/**
|
||||
* @brief Attach an CPU interrupt to a hardware source.
|
||||
* We have 4 steps to use an interrupt:
|
||||
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
|
||||
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
|
||||
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
|
||||
* 4.Enable interrupt in the module.
|
||||
*
|
||||
* @param int cpu_no : The CPU which the interrupt number belongs.
|
||||
*
|
||||
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
|
||||
*
|
||||
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifndef MAC2STR
|
||||
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
|
||||
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#endif
|
||||
|
||||
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
|
||||
|
||||
#ifdef ESP_PLATFORM
|
||||
// Remove in IDF v6.0 (IDF-7044)
|
||||
typedef enum {
|
||||
OK = 0,
|
||||
FAIL,
|
||||
PENDING,
|
||||
BUSY,
|
||||
CANCEL,
|
||||
} STATUS __attribute__((deprecated("Use ETS_STATUS instead")));
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_ETS_SYS_H_ */
|
||||
208
components/esp_rom/esp32c3/include/esp32c3/rom/gpio.h
Normal file
208
components/esp_rom/esp32c3/include/esp32c3/rom/gpio.h
Normal file
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/gpio_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup gpio_apis, uart configuration and communication related apis
|
||||
* @brief gpio apis
|
||||
*/
|
||||
|
||||
/** @addtogroup gpio_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
|
||||
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
|
||||
#define GPIO_ID_PIN0 0
|
||||
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
|
||||
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
|
||||
|
||||
#define GPIO_FUNC_IN_HIGH 0x1E
|
||||
#define GPIO_FUNC_IN_LOW 0x1F
|
||||
|
||||
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
|
||||
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
|
||||
|
||||
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
|
||||
|
||||
typedef enum {
|
||||
GPIO_PIN_INTR_DISABLE = 0,
|
||||
GPIO_PIN_INTR_POSEDGE = 1,
|
||||
GPIO_PIN_INTR_NEGEDGE = 2,
|
||||
GPIO_PIN_INTR_ANYEDGE = 3,
|
||||
GPIO_PIN_INTR_LOLEVEL = 4,
|
||||
GPIO_PIN_INTR_HILEVEL = 5
|
||||
} GPIO_INT_TYPE;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Change GPIO(0-21) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
|
||||
* There is no particular ordering guaranteed; so if the order of writes is significant,
|
||||
* calling code should divide a single call into multiple calls.
|
||||
*
|
||||
* @param uint32_t set_mask : the gpios that need high level.
|
||||
*
|
||||
* @param uint32_t clear_mask : the gpios that need low level.
|
||||
*
|
||||
* @param uint32_t enable_mask : the gpios that need be changed.
|
||||
*
|
||||
* @param uint32_t disable_mask : the gpios that need disable output.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
|
||||
|
||||
/**
|
||||
* @brief Sample the value of GPIO input pins(0-21) and returns a bitmask.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
|
||||
*/
|
||||
uint32_t gpio_input_get(void);
|
||||
|
||||
/**
|
||||
* @brief Set GPIO to wakeup the ESP32.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t i: gpio number.
|
||||
*
|
||||
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
|
||||
|
||||
/**
|
||||
* @brief disable GPIOs to wakeup the ESP32.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pin_wakeup_disable(void);
|
||||
|
||||
/**
|
||||
* @brief set gpio input to a signal, one gpio can input to several signals.
|
||||
*
|
||||
* @param uint32_t gpio : gpio number, 0-21
|
||||
* gpio == 0x1F, input 0 to signal
|
||||
* gpio == 0x1E, input 1 to signal
|
||||
*
|
||||
* @param uint32_t signal_idx : signal index.
|
||||
*
|
||||
* @param bool inv : the signal is inv or not
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
|
||||
|
||||
/**
|
||||
* @brief set signal output to gpio, one signal can output to several gpios.
|
||||
*
|
||||
* @param uint32_t gpio : gpio number, 0~21
|
||||
*
|
||||
* @param uint32_t signal_idx : signal index.
|
||||
* signal_idx == 0x80, cancel output put to the gpio
|
||||
*
|
||||
* @param bool out_inv : the signal output is invert or not
|
||||
*
|
||||
* @param bool oen_inv : the signal output enable is invert or not
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
|
||||
|
||||
/**
|
||||
* @brief Select pad as a gpio function from IOMUX.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_select_gpio(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Set pad driver capability.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @param uint32_t drv : 0-3
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
|
||||
|
||||
/**
|
||||
* @brief Pull up the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_pullup(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Pull down the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_pulldown(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Unhold the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_unhold(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Hold the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_hold(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief enable gpio pad input.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_input_enable(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief disable gpio pad input.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~21
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_input_disable(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
55
components/esp_rom/esp32c3/include/esp32c3/rom/hmac.h
Normal file
55
components/esp_rom/esp32c3/include/esp32c3/rom/hmac.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_HMAC_H_
|
||||
#define _ROM_HMAC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "efuse.h"
|
||||
|
||||
void ets_hmac_enable(void);
|
||||
|
||||
void ets_hmac_disable(void);
|
||||
|
||||
/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP)
|
||||
to digest a message.
|
||||
*/
|
||||
int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac);
|
||||
|
||||
/* Calculate a downstream HMAC message to temporarily enable JTAG, or
|
||||
to generate a Digital Signature data decryption key.
|
||||
|
||||
- purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
|
||||
or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
|
||||
|
||||
- key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6.
|
||||
This efuse block must have the corresponding purpose set in "purpose", or
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL.
|
||||
|
||||
The result of this HMAC calculation is only made available "downstream" to the
|
||||
corresponding hardware module, and cannot be accessed by software.
|
||||
*/
|
||||
int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose);
|
||||
|
||||
/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream().
|
||||
*
|
||||
* - purpose must match a previous call to ets_hmac_calculate_downstream().
|
||||
*
|
||||
* After this function is called, the corresponding internal operation (JTAG or DS) will no longer
|
||||
* have access to the generated key.
|
||||
*/
|
||||
int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _ROM_HMAC_H_
|
||||
84
components/esp_rom/esp32c3/include/esp32c3/rom/libc_stubs.h
Normal file
84
components/esp_rom/esp32c3/include/esp32c3/rom/libc_stubs.h
Normal file
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _ROM_LIBC_STUBS_H_
|
||||
#define _ROM_LIBC_STUBS_H_
|
||||
|
||||
#include <sys/lock.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <time.h>
|
||||
#include <reent.h>
|
||||
#include <errno.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
ESP32-C3 ROM code contains implementations of some of C library functions.
|
||||
Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
|
||||
implementation defined in the following struct.
|
||||
|
||||
The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to
|
||||
set the address
|
||||
|
||||
So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
|
||||
application must allocate syscall table structure for each CPU being used, and populate it with pointers
|
||||
to actual implementations of corresponding syscalls.
|
||||
*/
|
||||
|
||||
struct syscall_stub_table
|
||||
{
|
||||
struct _reent* (*__getreent)(void);
|
||||
void* (*_malloc_r)(struct _reent *r, size_t);
|
||||
void (*_free_r)(struct _reent *r, void*);
|
||||
void* (*_realloc_r)(struct _reent *r, void*, size_t);
|
||||
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
|
||||
void (*_abort)(void);
|
||||
int (*_system_r)(struct _reent *r, const char*);
|
||||
int (*_rename_r)(struct _reent *r, const char*, const char*);
|
||||
clock_t (*_times_r)(struct _reent *r, struct tms *);
|
||||
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
|
||||
void (*_raise_r)(struct _reent *r);
|
||||
int (*_unlink_r)(struct _reent *r, const char*);
|
||||
int (*_link_r)(struct _reent *r, const char*, const char*);
|
||||
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
|
||||
int (*_fstat_r)(struct _reent *r, int, struct stat *);
|
||||
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
|
||||
int (*_getpid_r)(struct _reent *r);
|
||||
int (*_kill_r)(struct _reent *r, int, int);
|
||||
void (*_exit_r)(struct _reent *r, int);
|
||||
int (*_close_r)(struct _reent *r, int);
|
||||
int (*_open_r)(struct _reent *r, const char *, int, int);
|
||||
int (*_write_r)(struct _reent *r, int, const void *, int);
|
||||
int (*_lseek_r)(struct _reent *r, int, int, int);
|
||||
int (*_read_r)(struct _reent *r, int, void *, int);
|
||||
void (*_retarget_lock_init)(_LOCK_T *lock);
|
||||
void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
|
||||
void (*_retarget_lock_close)(_LOCK_T lock);
|
||||
void (*_retarget_lock_close_recursive)(_LOCK_T lock);
|
||||
void (*_retarget_lock_acquire)(_LOCK_T lock);
|
||||
void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
|
||||
int (*_retarget_lock_try_acquire)(_LOCK_T lock);
|
||||
int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
|
||||
void (*_retarget_lock_release)(_LOCK_T lock);
|
||||
void (*_retarget_lock_release_recursive)(_LOCK_T lock);
|
||||
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap);
|
||||
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
|
||||
void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((__noreturn__));
|
||||
void (*__sinit) (struct _reent *r);
|
||||
void (*_cleanup_r) (struct _reent* r);
|
||||
};
|
||||
|
||||
extern struct syscall_stub_table *syscall_table_ptr;
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_LIBC_STUBS_H_ */
|
||||
132
components/esp_rom/esp32c3/include/esp32c3/rom/lldesc.h
Normal file
132
components/esp_rom/esp32c3/include/esp32c3/rom/lldesc.h
Normal file
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_LLDESC_H_
|
||||
#define _ROM_LLDESC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "sys/queue.h"
|
||||
#include "esp_rom_lldesc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LLDESC_TX_MBLK_SIZE 268 /* */
|
||||
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
|
||||
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
|
||||
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
|
||||
#ifdef ESP_MAC_5
|
||||
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
|
||||
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
|
||||
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
|
||||
#else
|
||||
#ifdef SBUF_RXTX
|
||||
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
|
||||
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
|
||||
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
|
||||
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
|
||||
#endif
|
||||
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
|
||||
|
||||
#ifdef IEEE80211_RX_AMPDU
|
||||
#define LLDESC_RX_MBLK_NUM 30
|
||||
#else
|
||||
#define LLDESC_RX_MBLK_NUM 10
|
||||
#endif /*IEEE80211_RX_AMPDU*/
|
||||
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
|
||||
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
|
||||
#endif /* !ESP_MAC_5 */
|
||||
|
||||
typedef struct tx_ampdu_entry_s {
|
||||
uint32_t sub_len : 12,
|
||||
dili_num : 7,
|
||||
: 1,
|
||||
null_byte: 2,
|
||||
data : 1,
|
||||
enc : 1,
|
||||
seq : 8;
|
||||
} tx_ampdu_entry_t;
|
||||
|
||||
typedef struct lldesc_chain_s {
|
||||
lldesc_t *head;
|
||||
lldesc_t *tail;
|
||||
} lldesc_chain_t;
|
||||
|
||||
#ifdef SBUF_RXTX
|
||||
enum sbuf_mask_s {
|
||||
SBUF_MOVE_NO = 0,
|
||||
SBUF_MOVE_TX2RX,
|
||||
SBUF_MOVE_RX2TX,
|
||||
} ;
|
||||
|
||||
#define SBUF_MOVE_STEP 8
|
||||
#endif
|
||||
#define LLDESC_SIZE sizeof(struct lldesc_s)
|
||||
|
||||
/* SLC Descriptor */
|
||||
#define LLDESC_OWNER_MASK 0x80000000
|
||||
#define LLDESC_OWNER_SHIFT 31
|
||||
#define LLDESC_SW_OWNED 0
|
||||
#define LLDESC_HW_OWNED 1
|
||||
|
||||
#define LLDESC_EOF_MASK 0x40000000
|
||||
#define LLDESC_EOF_SHIFT 30
|
||||
|
||||
#define LLDESC_SOSF_MASK 0x20000000
|
||||
#define LLDESC_SOSF_SHIFT 29
|
||||
|
||||
#define LLDESC_LENGTH_MASK 0x00fff000
|
||||
#define LLDESC_LENGTH_SHIFT 12
|
||||
|
||||
#define LLDESC_SIZE_MASK 0x00000fff
|
||||
#define LLDESC_SIZE_SHIFT 0
|
||||
|
||||
#define LLDESC_ADDR_MASK 0x000fffff
|
||||
|
||||
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
|
||||
{
|
||||
lldesc_t *ds = head;
|
||||
uint32_t len = 0;
|
||||
|
||||
while (ds) {
|
||||
len += ds->length;
|
||||
ds = STAILQ_NEXT(ds, qe);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
|
||||
{
|
||||
ds->owner = owner;
|
||||
ds->eof = eof;
|
||||
ds->sosf = sosf;
|
||||
ds->length = len;
|
||||
}
|
||||
|
||||
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \
|
||||
(_desc)->owner = (_owner); \
|
||||
(_desc)->eof = (_eof); \
|
||||
(_desc)->sosf = (_sosf); \
|
||||
(_desc)->length = (_len); \
|
||||
} while(0)
|
||||
|
||||
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
|
||||
|
||||
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
|
||||
|
||||
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_LLDESC_H_ */
|
||||
43
components/esp_rom/esp32c3/include/esp32c3/rom/md5_hash.h
Normal file
43
components/esp_rom/esp32c3/include/esp32c3/rom/md5_hash.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2003-2005, Jouni Malinen <j@w1.fi>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* MD5 internal definitions
|
||||
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of BSD
|
||||
* license.
|
||||
*
|
||||
* See README and COPYING for more details.
|
||||
*/
|
||||
|
||||
#ifndef _ROM_MD5_HASH_H_
|
||||
#define _ROM_MD5_HASH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct MD5Context {
|
||||
uint32_t buf[4];
|
||||
uint32_t bits[2];
|
||||
uint8_t in[64];
|
||||
};
|
||||
|
||||
void MD5Init(struct MD5Context *context);
|
||||
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
|
||||
void MD5Final(unsigned char digest[16], struct MD5Context *context);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_MD5_HASH_H_ */
|
||||
91
components/esp_rom/esp32c3/include/esp32c3/rom/rom_layout.h
Normal file
91
components/esp_rom/esp32c3/include/esp32c3/rom/rom_layout.h
Normal file
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SUPPORT_BTDM 1
|
||||
#define SUPPORT_WIFI 1
|
||||
#define SUPPORT_USB_DWCOTG 0
|
||||
|
||||
/* Structure and functions for returning ROM global layout
|
||||
*
|
||||
* This is for address symbols defined in the linker script, which may change during ECOs.
|
||||
*/
|
||||
typedef struct {
|
||||
void *dram0_stack_shared_mem_start;
|
||||
void *dram0_rtos_reserved_start;
|
||||
void *stack_sentry;
|
||||
void *stack;
|
||||
void *stack_sentry_app;
|
||||
void *stack_app;
|
||||
|
||||
/* BTDM data */
|
||||
#if SUPPORT_BTDM
|
||||
void *data_start_btdm;
|
||||
void *data_end_btdm;
|
||||
void *bss_start_btdm;
|
||||
void *bss_end_btdm;
|
||||
void *data_start_btdm_rom;
|
||||
void *data_end_btdm_rom;
|
||||
void *data_start_interface_btdm;
|
||||
void *data_end_interface_btdm;
|
||||
void *bss_start_interface_btdm;
|
||||
void *bss_end_interface_btdm;
|
||||
#endif
|
||||
|
||||
/* Other DRAM ranges */
|
||||
#if SUPPORT_BTDM || SUPPORT_WIFI
|
||||
void *dram_start_phyrom;
|
||||
void *dram_end_phyrom;
|
||||
#endif
|
||||
|
||||
#if SUPPORT_WIFI
|
||||
void *dram_start_coexist;
|
||||
void *dram_end_coexist;
|
||||
void *dram_start_net80211;
|
||||
void *dram_end_net80211;
|
||||
void *dram_start_pp;
|
||||
void *dram_end_pp;
|
||||
void *data_start_interface_coexist;
|
||||
void *data_end_interface_coexist;
|
||||
void *bss_start_interface_coexist;
|
||||
void *bss_end_interface_coexist;
|
||||
void *data_start_interface_net80211;
|
||||
void *data_end_interface_net80211;
|
||||
void *bss_start_interface_net80211;
|
||||
void *bss_end_interface_net80211;
|
||||
void *data_start_interface_pp;
|
||||
void *data_end_interface_pp;
|
||||
void *bss_start_interface_pp;
|
||||
void *bss_end_interface_pp;
|
||||
#endif
|
||||
|
||||
#if SUPPORT_USB_DWCOTG
|
||||
void *dram_start_usb_dwcotg_rom;
|
||||
void *dram_end_usb_dwcotg_rom;
|
||||
#else
|
||||
//Two reserved members are defined here, so the structure will not be broken,
|
||||
//please keep in mind that there is no memory can be released between
|
||||
//dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom.
|
||||
void *dram_start_usb_reserved_rom;
|
||||
void *dram_end_usb_reserved_rom;
|
||||
#endif
|
||||
|
||||
void *dram_start_uart_rom;
|
||||
void *dram_end_uart_rom;
|
||||
} ets_rom_layout_t;
|
||||
|
||||
extern const ets_rom_layout_t * const ets_rom_layout_p;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
38
components/esp_rom/esp32c3/include/esp32c3/rom/rsa_pss.h
Normal file
38
components/esp_rom/esp32c3/include/esp32c3/rom/rsa_pss.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_RSA_PSS_H_
|
||||
#define _ROM_RSA_PSS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ETS_SIG_LEN 384 /* Bytes */
|
||||
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
|
||||
|
||||
typedef struct {
|
||||
uint8_t n[384]; /* Public key modulus */
|
||||
uint32_t e; /* Public key exponent */
|
||||
uint8_t rinv[384];
|
||||
uint32_t mdash;
|
||||
} ets_rsa_pubkey_t;
|
||||
|
||||
bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
|
||||
|
||||
void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
|
||||
|
||||
bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
247
components/esp_rom/esp32c3/include/esp32c3/rom/rtc.h
Normal file
247
components/esp_rom/esp32c3/include/esp32c3/rom/rtc.h
Normal file
@@ -0,0 +1,247 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_RTC_H_
|
||||
#define _ROM_RTC_H_
|
||||
|
||||
#include "ets_sys.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/reset_reasons.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup rtc_apis, rtc registers and memory related apis
|
||||
* @brief rtc apis
|
||||
*/
|
||||
|
||||
/** @addtogroup rtc_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**************************************************************************************
|
||||
* Note: *
|
||||
* Some Rtc memory and registers are used, in ROM or in internal library. *
|
||||
* Please do not use reserved or used rtc memory or registers. *
|
||||
* *
|
||||
*************************************************************************************
|
||||
* RTC Memory & Store Register usage
|
||||
*************************************************************************************
|
||||
* rtc memory addr type size usage
|
||||
* 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
|
||||
* 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
|
||||
*
|
||||
* 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
|
||||
*
|
||||
*************************************************************************************
|
||||
* RTC store registers usage
|
||||
* RTC_CNTL_STORE0_REG Reserved
|
||||
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
|
||||
* RTC_CNTL_STORE2_REG Boot time, low word
|
||||
* RTC_CNTL_STORE3_REG Boot time, high word
|
||||
* RTC_CNTL_STORE4_REG External XTAL frequency
|
||||
* RTC_CNTL_STORE5_REG APB bus frequency
|
||||
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
|
||||
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
|
||||
*************************************************************************************
|
||||
*/
|
||||
|
||||
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
|
||||
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
|
||||
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
|
||||
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
|
||||
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
|
||||
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
|
||||
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
|
||||
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
|
||||
|
||||
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
|
||||
|
||||
|
||||
typedef enum {
|
||||
AWAKE = 0, //<CPU ON
|
||||
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
|
||||
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
|
||||
} SLEEP_MODE;
|
||||
|
||||
typedef enum {
|
||||
NO_MEAN = 0,
|
||||
POWERON_RESET = 1, /**<1, Vbat power on reset*/
|
||||
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
|
||||
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
|
||||
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
|
||||
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
|
||||
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
|
||||
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
|
||||
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
|
||||
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
|
||||
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
|
||||
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
|
||||
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
|
||||
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
|
||||
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
|
||||
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
|
||||
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
|
||||
} RESET_REASON;
|
||||
|
||||
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
|
||||
|
||||
typedef enum {
|
||||
NO_SLEEP = 0,
|
||||
EXT_EVENT0_TRIG = BIT0,
|
||||
EXT_EVENT1_TRIG = BIT1,
|
||||
GPIO_TRIG = BIT2,
|
||||
TIMER_EXPIRE = BIT3,
|
||||
SDIO_TRIG = BIT4,
|
||||
MAC_TRIG = BIT5,
|
||||
UART0_TRIG = BIT6,
|
||||
UART1_TRIG = BIT7,
|
||||
TOUCH_TRIG = BIT8,
|
||||
SAR_TRIG = BIT9,
|
||||
BT_TRIG = BIT10,
|
||||
RISCV_TRIG = BIT11,
|
||||
XTAL_DEAD_TRIG = BIT12,
|
||||
RISCV_TRAP_TRIG = BIT13,
|
||||
USB_TRIG = BIT14
|
||||
} WAKEUP_REASON;
|
||||
|
||||
typedef enum {
|
||||
DISEN_WAKEUP = NO_SLEEP,
|
||||
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
|
||||
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
|
||||
GPIO_TRIG_EN = GPIO_TRIG,
|
||||
TIMER_EXPIRE_EN = TIMER_EXPIRE,
|
||||
SDIO_TRIG_EN = SDIO_TRIG,
|
||||
MAC_TRIG_EN = MAC_TRIG,
|
||||
UART0_TRIG_EN = UART0_TRIG,
|
||||
UART1_TRIG_EN = UART1_TRIG,
|
||||
TOUCH_TRIG_EN = TOUCH_TRIG,
|
||||
SAR_TRIG_EN = SAR_TRIG,
|
||||
BT_TRIG_EN = BT_TRIG,
|
||||
RISCV_TRIG_EN = RISCV_TRIG,
|
||||
XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
|
||||
RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
|
||||
USB_TRIG_EN = USB_TRIG
|
||||
} WAKEUP_ENABLE;
|
||||
|
||||
/**
|
||||
* @brief Get the reset reason for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return RESET_REASON
|
||||
*/
|
||||
RESET_REASON rtc_get_reset_reason(int cpu_no);
|
||||
|
||||
/**
|
||||
* @brief Get the wakeup cause for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return WAKEUP_REASON
|
||||
*/
|
||||
WAKEUP_REASON rtc_get_wakeup_cause(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Suppress ROM log by setting specific RTC control register.
|
||||
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void rtc_suppress_rom_log(void)
|
||||
{
|
||||
/* To disable logging in the ROM, only the least significant bit of the register is used,
|
||||
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
|
||||
* you need to write to this register in the same format.
|
||||
* Namely, the upper 16 bits and lower should be the same.
|
||||
*/
|
||||
REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void set_rtc_memory_crc(void);
|
||||
|
||||
/**
|
||||
* @brief Fetch entry from RTC memory and RTC STORE reg
|
||||
*
|
||||
* @param uint32_t * entry_addr : the address to save entry
|
||||
*
|
||||
* @param RESET_REASON reset_reason : reset reason this time
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset(void);
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset_cpu(int cpu_no);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_RTC_H_ */
|
||||
105
components/esp_rom/esp32c3/include/esp32c3/rom/secure_boot.h
Normal file
105
components/esp_rom/esp32c3/include/esp32c3/rom/secure_boot.h
Normal file
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "ets_sys.h"
|
||||
#include "rsa_pss.h"
|
||||
#include "esp_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
|
||||
typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
|
||||
typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
|
||||
|
||||
/* Anti-FI measure: use full words for success/fail, instead of
|
||||
0/non-zero
|
||||
*/
|
||||
typedef enum {
|
||||
SB_SUCCESS = 0x3A5A5AA5,
|
||||
SB_FAILED = 0x7533885E,
|
||||
} ets_secure_boot_status_t;
|
||||
|
||||
/* Verify bootloader image (reconfigures cache to map),
|
||||
with key digests provided as parameters.)
|
||||
|
||||
Can be used to verify secure boot status before enabling
|
||||
secure boot permanently.
|
||||
|
||||
If stage_load parameter is true, bootloader is copied into staging
|
||||
buffer in RAM at the same time.
|
||||
|
||||
If result is SB_SUCCESS, the "simple hash" of the bootloader is
|
||||
copied into verified_hash.
|
||||
*/
|
||||
ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
|
||||
|
||||
/* Read key digests from efuse. Any revoked/missing digests will be
|
||||
marked as NULL
|
||||
*/
|
||||
ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
|
||||
|
||||
/* Verify supplied signature against supplied digest, using
|
||||
supplied trusted key digests.
|
||||
|
||||
Doesn't reconfigure cache or any other hardware access except for RSA peripheral.
|
||||
|
||||
If result is SB_SUCCESS, the image_digest value is copied into verified_digest.
|
||||
*/
|
||||
ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
|
||||
|
||||
/* Revoke a public key digest in efuse.
|
||||
@param index Digest to revoke. Must be 0, 1 or 2.
|
||||
*/
|
||||
void ets_secure_boot_revoke_public_key_digest(int index);
|
||||
|
||||
#define CRC_SIGN_BLOCK_LEN 1196
|
||||
#define SIG_BLOCK_PADDING 4096
|
||||
#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
|
||||
|
||||
/* Secure Boot V2 signature block
|
||||
|
||||
(Up to 3 in a signature sector are appended to the image)
|
||||
*/
|
||||
struct ets_secure_boot_sig_block {
|
||||
uint8_t magic_byte;
|
||||
uint8_t version;
|
||||
uint8_t _reserved1;
|
||||
uint8_t _reserved2;
|
||||
uint8_t image_digest[32];
|
||||
ets_rsa_pubkey_t key;
|
||||
uint8_t signature[384];
|
||||
uint32_t block_crc;
|
||||
uint8_t _padding[16];
|
||||
};
|
||||
|
||||
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
|
||||
|
||||
#define SECURE_BOOT_NUM_BLOCKS 3
|
||||
|
||||
/* V2 Secure boot signature sector (up to 3 blocks) */
|
||||
struct ets_secure_boot_signature {
|
||||
ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
|
||||
uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
|
||||
};
|
||||
|
||||
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
|
||||
|
||||
#define MAX_KEY_DIGESTS 3
|
||||
|
||||
struct ets_secure_boot_key_digests {
|
||||
const void *key_digests[MAX_KEY_DIGESTS];
|
||||
bool allow_key_revoke;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
53
components/esp_rom/esp32c3/include/esp32c3/rom/sha.h
Normal file
53
components/esp_rom/esp32c3/include/esp32c3/rom/sha.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _ROM_SHA_H_
|
||||
#define _ROM_SHA_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "ets_sys.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SHA1 = 0,
|
||||
SHA2_224,
|
||||
SHA2_256,
|
||||
SHA_TYPE_MAX
|
||||
} SHA_TYPE;
|
||||
|
||||
typedef struct SHAContext {
|
||||
bool start;
|
||||
bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
|
||||
SHA_TYPE type;
|
||||
uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16
|
||||
unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128
|
||||
uint32_t total_bits[4];
|
||||
} SHA_CTX;
|
||||
|
||||
void ets_sha_enable(void);
|
||||
|
||||
void ets_sha_disable(void);
|
||||
|
||||
ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
|
||||
|
||||
ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
|
||||
|
||||
void ets_sha_get_state(SHA_CTX *ctx);
|
||||
|
||||
void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
|
||||
|
||||
void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
|
||||
|
||||
ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_SHA_H_ */
|
||||
465
components/esp_rom/esp32c3/include/esp32c3/rom/spi_flash.h
Normal file
465
components/esp_rom/esp32c3/include/esp32c3/rom/spi_flash.h
Normal file
@@ -0,0 +1,465 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
|
||||
|
||||
#define SPI0_R_QIO_DUMMY_CYCLELEN 5
|
||||
#define SPI0_R_QIO_ADDR_BITSLEN 23
|
||||
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI0_R_DIO_DUMMY_CYCLELEN 3
|
||||
#define SPI0_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI0_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
|
||||
#define SPI1_R_QIO_ADDR_BITSLEN 23
|
||||
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
|
||||
#define SPI1_R_DIO_ADDR_BITSLEN 23
|
||||
#define SPI1_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI1_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B
|
||||
|
||||
//SPI address register
|
||||
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
|
||||
|
||||
typedef void (* spi_flash_func_t)(void);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
|
||||
|
||||
typedef struct {
|
||||
uint32_t read_sub_len;
|
||||
uint32_t write_sub_len;
|
||||
spi_flash_op_t unlock;
|
||||
spi_flash_erase_t erase_sector;
|
||||
spi_flash_erase_t erase_block;
|
||||
spi_flash_rd_t read;
|
||||
spi_flash_wr_t write;
|
||||
spi_flash_ewr_t encrypt_write;
|
||||
spi_flash_func_t check_sus;
|
||||
spi_flash_wren_t wren;
|
||||
spi_flash_op_t wait_idle;
|
||||
} spiflash_legacy_funcs_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t data_length;
|
||||
uint8_t read_cmd0;
|
||||
uint8_t read_cmd1;
|
||||
uint8_t write_cmd;
|
||||
uint16_t data_mask;
|
||||
uint16_t data;
|
||||
} esp_rom_spiflash_common_cmd_t;
|
||||
|
||||
/**
|
||||
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @param uint8_t legacy: always keeping false.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
|
||||
|
||||
/**
|
||||
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t *status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
|
||||
|
||||
/**
|
||||
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t *status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
|
||||
|
||||
/**
|
||||
* @brief Write status to Flash status register.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t status_value : Value to .
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
|
||||
|
||||
/**
|
||||
* @brief Use a command to Read Flash status register.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t*status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
|
||||
|
||||
/**
|
||||
* @brief Config SPI Flash read mode when init.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
|
||||
*
|
||||
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Config SPI Flash clock divisor.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t freqdiv: clock divisor.
|
||||
*
|
||||
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
|
||||
|
||||
/**
|
||||
* @brief Clear all SR bits except QE bit.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
|
||||
|
||||
/**
|
||||
* @brief Clear all SR bits except QE bit.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
|
||||
|
||||
/**
|
||||
* @brief Update SPI Flash parameter.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
|
||||
*
|
||||
* @param uint32_t chip_size : The Flash size.
|
||||
*
|
||||
* @param uint32_t block_size : The Flash block size.
|
||||
*
|
||||
* @param uint32_t sector_size : The Flash sector size.
|
||||
*
|
||||
* @param uint32_t page_size : The Flash page size.
|
||||
*
|
||||
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
|
||||
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
|
||||
|
||||
/**
|
||||
* @brief Erase whole flash chip.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
|
||||
|
||||
/**
|
||||
* @brief Erase a 64KB block of flash
|
||||
* Uses SPI flash command D8H.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t block_num : Which block to erase.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
|
||||
|
||||
/**
|
||||
* @brief Erase a sector of flash.
|
||||
* Uses SPI flash command 20H.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t sector_num : Which sector to erase.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
|
||||
|
||||
/**
|
||||
* @brief Erase some sectors.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
|
||||
*
|
||||
* @param uint32_t area_len : Length to erase, should be sector aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
|
||||
|
||||
/**
|
||||
* @brief Write Data to Flash, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
|
||||
*
|
||||
* @param const uint32_t *src : The pointer to data which is to write.
|
||||
*
|
||||
* @param uint32_t len : Length to write, should be 4 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
|
||||
|
||||
/**
|
||||
* @brief Read Data from Flash, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
|
||||
*
|
||||
* @param uint32_t *dest : The buf to read the data.
|
||||
*
|
||||
* @param uint32_t len : Length to read, should be 4 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
|
||||
|
||||
/**
|
||||
* @brief SPI1 go into encrypto mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_write_encrypted_enable(void);
|
||||
|
||||
/**
|
||||
* @brief SPI1 go out of encrypto mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_write_encrypted_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Write data to flash with transparent encryption.
|
||||
* @note Sectors to be written should already be erased.
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
|
||||
*
|
||||
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
|
||||
* be 32 bit aligned and the content of the data will be
|
||||
* modified by the encryption function.
|
||||
*
|
||||
* @param uint32_t len : Length to write, should be 32 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
|
||||
|
||||
|
||||
/** @brief Wait until SPI flash write operation is complete
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* Reads the Write In Progress bit of the SPI flash status register,
|
||||
* repeats until this bit is zero (indicating write complete).
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
|
||||
|
||||
|
||||
/** @brief Enable Quad I/O pin functions
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* Sets the HD & WP pin functions for Quad I/O modes, based on the
|
||||
* efuse SPI pin configuration.
|
||||
*
|
||||
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
|
||||
*
|
||||
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
|
||||
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
|
||||
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
|
||||
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
|
||||
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
|
||||
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
|
||||
*/
|
||||
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
|
||||
|
||||
/**
|
||||
* @brief Clear WEL bit unconditionally.
|
||||
*
|
||||
* @return always ESP_ROM_SPIFLASH_RESULT_OK
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Set WREN bit.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @return always ESP_ROM_SPIFLASH_RESULT_OK
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
|
||||
*
|
||||
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
|
||||
|
||||
/**
|
||||
* @brief Set SPI Flash pad drivers.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t wp_gpio_num: WP gpio number.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
|
||||
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
|
||||
* Values usually read from flash by rom code, function usually called by rom code.
|
||||
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
|
||||
|
||||
/**
|
||||
* @brief Select SPI Flash function for pads.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
|
||||
|
||||
/**
|
||||
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
|
||||
*
|
||||
* @return uint16_t 0 : do not send command any more.
|
||||
* 1 : go to the next command.
|
||||
* n > 1 : skip (n - 1) commands.
|
||||
*/
|
||||
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
|
||||
|
||||
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
99
components/esp_rom/esp32c3/include/esp32c3/rom/tjpgd.h
Normal file
99
components/esp_rom/esp32c3/include/esp32c3/rom/tjpgd.h
Normal file
@@ -0,0 +1,99 @@
|
||||
/*----------------------------------------------------------------------------/
|
||||
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------*/
|
||||
#ifndef _TJPGDEC
|
||||
#define _TJPGDEC
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* System Configurations */
|
||||
|
||||
#define JD_SZBUF 512 /* Size of stream input buffer */
|
||||
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
|
||||
#define JD_USE_SCALE 1 /* Use descaling feature for output */
|
||||
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* These types must be 16-bit, 32-bit or larger integer */
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* These types must be 8-bit integer */
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
/* These types must be 16-bit integer */
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
|
||||
/* These types must be 32-bit integer */
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
|
||||
/* Error code */
|
||||
typedef enum {
|
||||
JDR_OK = 0, /* 0: Succeeded */
|
||||
JDR_INTR, /* 1: Interrupted by output function */
|
||||
JDR_INP, /* 2: Device error or wrong termination of input stream */
|
||||
JDR_MEM1, /* 3: Insufficient memory pool for the image */
|
||||
JDR_MEM2, /* 4: Insufficient stream input buffer */
|
||||
JDR_PAR, /* 5: Parameter error */
|
||||
JDR_FMT1, /* 6: Data format error (may be damaged data) */
|
||||
JDR_FMT2, /* 7: Right format but not supported */
|
||||
JDR_FMT3 /* 8: Not supported JPEG standard */
|
||||
} JRESULT;
|
||||
|
||||
|
||||
|
||||
/* Rectangular structure */
|
||||
typedef struct {
|
||||
WORD left, right, top, bottom;
|
||||
} JRECT;
|
||||
|
||||
|
||||
|
||||
/* Decompressor object structure */
|
||||
typedef struct JDEC JDEC;
|
||||
struct JDEC {
|
||||
UINT dctr; /* Number of bytes available in the input buffer */
|
||||
BYTE *dptr; /* Current data read ptr */
|
||||
BYTE *inbuf; /* Bit stream input buffer */
|
||||
BYTE dmsk; /* Current bit in the current read byte */
|
||||
BYTE scale; /* Output scaling ratio */
|
||||
BYTE msx, msy; /* MCU size in unit of block (width, height) */
|
||||
BYTE qtid[3]; /* Quantization table ID of each component */
|
||||
SHORT dcv[3]; /* Previous DC element of each component */
|
||||
WORD nrst; /* Restart interval */
|
||||
UINT width, height; /* Size of the input image (pixel) */
|
||||
BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
|
||||
WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */
|
||||
BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
|
||||
LONG *qttbl[4]; /* Dequaitizer tables [id] */
|
||||
void *workbuf; /* Working buffer for IDCT and RGB output */
|
||||
BYTE *mcubuf; /* Working buffer for the MCU */
|
||||
void *pool; /* Pointer to available memory pool */
|
||||
UINT sz_pool; /* Size of memory pool (bytes available) */
|
||||
UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */
|
||||
void *device; /* Pointer to I/O device identifier for the session */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* TJpgDec API functions */
|
||||
JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *);
|
||||
JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TJPGDEC */
|
||||
322
components/esp_rom/esp32c3/include/esp32c3/rom/uart.h
Normal file
322
components/esp_rom/esp32c3/include/esp32c3/rom/uart.h
Normal file
@@ -0,0 +1,322 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_UART_H_
|
||||
#define _ROM_UART_H_
|
||||
|
||||
#include "esp_types.h"
|
||||
#include "esp_attr.h"
|
||||
#include "ets_sys.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/uart_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup uart_apis, uart configuration and communication related apis
|
||||
* @brief uart apis
|
||||
*/
|
||||
|
||||
/** @addtogroup uart_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RX_BUFF_SIZE 0x400
|
||||
#define TX_BUFF_SIZE 100
|
||||
|
||||
//uart int enable register ctrl bits
|
||||
#define UART_RCV_INTEN BIT0
|
||||
#define UART_TRX_INTEN BIT1
|
||||
#define UART_LINE_STATUS_INTEN BIT2
|
||||
|
||||
//uart int identification ctrl bits
|
||||
#define UART_INT_FLAG_MASK 0x0E
|
||||
|
||||
//uart fifo ctrl bits
|
||||
#define UART_CLR_RCV_FIFO BIT1
|
||||
#define UART_CLR_TRX_FIFO BIT2
|
||||
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
|
||||
|
||||
//uart line control bits
|
||||
#define UART_DIV_LATCH_ACCESS_BIT BIT7
|
||||
|
||||
//uart line status bits
|
||||
#define UART_RCV_DATA_RDY_FLAG BIT0
|
||||
#define UART_RCV_OVER_FLOW_FLAG BIT1
|
||||
#define UART_RCV_PARITY_ERR_FLAG BIT2
|
||||
#define UART_RCV_FRAME_ERR_FLAG BIT3
|
||||
#define UART_BRK_INT_FLAG BIT4
|
||||
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
|
||||
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
|
||||
#define UART_RCV_ERR_FLAG BIT7
|
||||
|
||||
//send and receive message frame head
|
||||
#define FRAME_FLAG 0x7E
|
||||
|
||||
typedef enum {
|
||||
UART_LINE_STATUS_INT_FLAG = 0x06,
|
||||
UART_RCV_FIFO_INT_FLAG = 0x04,
|
||||
UART_RCV_TMOUT_INT_FLAG = 0x0C,
|
||||
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
|
||||
} UartIntType; //consider bit0 for int_flag
|
||||
|
||||
typedef enum {
|
||||
RCV_ONE_BYTE = 0x0,
|
||||
RCV_FOUR_BYTE = 0x1,
|
||||
RCV_EIGHT_BYTE = 0x2,
|
||||
RCV_FOURTEEN_BYTE = 0x3
|
||||
} UartRcvFifoTrgLvl;
|
||||
|
||||
typedef enum {
|
||||
FIVE_BITS = 0x0,
|
||||
SIX_BITS = 0x1,
|
||||
SEVEN_BITS = 0x2,
|
||||
EIGHT_BITS = 0x3
|
||||
} UartBitsNum4Char;
|
||||
|
||||
typedef enum {
|
||||
ONE_STOP_BIT = 1,
|
||||
ONE_HALF_STOP_BIT = 2,
|
||||
TWO_STOP_BIT = 3
|
||||
} UartStopBitsNum;
|
||||
|
||||
typedef enum {
|
||||
NONE_BITS = 0,
|
||||
ODD_BITS = 2,
|
||||
EVEN_BITS = 3
|
||||
|
||||
} UartParityMode;
|
||||
|
||||
typedef enum {
|
||||
STICK_PARITY_DIS = 0,
|
||||
STICK_PARITY_EN = 2
|
||||
} UartExistParity;
|
||||
|
||||
typedef enum {
|
||||
BIT_RATE_9600 = 9600,
|
||||
BIT_RATE_19200 = 19200,
|
||||
BIT_RATE_38400 = 38400,
|
||||
BIT_RATE_57600 = 57600,
|
||||
BIT_RATE_115200 = 115200,
|
||||
BIT_RATE_230400 = 230400,
|
||||
BIT_RATE_460800 = 460800,
|
||||
BIT_RATE_921600 = 921600
|
||||
} UartBautRate;
|
||||
|
||||
typedef enum {
|
||||
NONE_CTRL,
|
||||
HARDWARE_CTRL,
|
||||
XON_XOFF_CTRL
|
||||
} UartFlowCtrl;
|
||||
|
||||
typedef enum {
|
||||
EMPTY,
|
||||
UNDER_WRITE,
|
||||
WRITE_OVER
|
||||
} RcvMsgBuffState;
|
||||
|
||||
typedef struct {
|
||||
uint8_t *pRcvMsgBuff;
|
||||
uint8_t *pWritePos;
|
||||
uint8_t *pReadPos;
|
||||
uint8_t TrigLvl;
|
||||
RcvMsgBuffState BuffState;
|
||||
} RcvMsgBuff;
|
||||
|
||||
typedef struct {
|
||||
uint32_t TrxBuffSize;
|
||||
uint8_t *pTrxBuff;
|
||||
} TrxMsgBuff;
|
||||
|
||||
typedef enum {
|
||||
BAUD_RATE_DET,
|
||||
WAIT_SYNC_FRM,
|
||||
SRCH_MSG_HEAD,
|
||||
RCV_MSG_BODY,
|
||||
RCV_ESC_CHAR,
|
||||
} RcvMsgState;
|
||||
|
||||
typedef struct {
|
||||
UartBautRate baut_rate;
|
||||
UartBitsNum4Char data_bits;
|
||||
UartExistParity exist_parity;
|
||||
UartParityMode parity; // chip size in byte
|
||||
UartStopBitsNum stop_bits;
|
||||
UartFlowCtrl flow_ctrl;
|
||||
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
|
||||
RcvMsgBuff rcv_buff;
|
||||
// TrxMsgBuff trx_buff;
|
||||
RcvMsgState rcv_state;
|
||||
int received;
|
||||
} UartDevice;
|
||||
|
||||
/**
|
||||
* @brief Init uart device struct value and reset uart0/uart1 rx.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uartAttach(void *rxBuffer);
|
||||
|
||||
/**
|
||||
* @brief Init uart0 or uart1 for UART download booting mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, else for UART1.
|
||||
*
|
||||
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Uart_Init(uint8_t uart_no, uint32_t clock);
|
||||
|
||||
/**
|
||||
* @brief Modify uart baudrate.
|
||||
* This function will reset RX/TX fifo for uart.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
|
||||
|
||||
/**
|
||||
* @brief Output a char to printf channel, wait until fifo not full.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS uart_tx_one_char(uint8_t TxChar);
|
||||
|
||||
/**
|
||||
* @brief Output a char to message exchange channel, wait until fifo not full.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS uart_tx_one_char2(uint8_t TxChar);
|
||||
|
||||
/**
|
||||
* @brief Wait until uart tx full empty.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void uart_tx_flush(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Wait until uart tx full empty and the last char send ok.
|
||||
*
|
||||
* @param uart_no : 0 for UART0, 1 for UART1
|
||||
*
|
||||
* The function defined in ROM code has a bug, so we define the correct version
|
||||
* here for compatibility.
|
||||
*/
|
||||
void uart_tx_wait_idle(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Get an input char from message channel.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pRxChar : the pointer to store the char.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS uart_rx_one_char(uint8_t *pRxChar);
|
||||
|
||||
/**
|
||||
* @brief Get an input char from message channel, wait until successful.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return char : input char value.
|
||||
*/
|
||||
char uart_rx_one_char_block(void);
|
||||
|
||||
/**
|
||||
* @brief Get an input string line from message channel.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pString : the pointer to store the string.
|
||||
*
|
||||
* @param uint8_t MaxStrlen : the max string length, include '\0'.
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
|
||||
|
||||
/**
|
||||
* @brief Get an char from receive buffer.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
|
||||
*
|
||||
* @param uint8_t *pRxByte : the pointer to store the char.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
|
||||
|
||||
/**
|
||||
* @brief Get uart configuration struct.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UartDevice * : uart configuration struct pointer.
|
||||
*/
|
||||
UartDevice *GetUartDevice(void);
|
||||
|
||||
/**
|
||||
* @brief Send an packet to download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *p : the pointer to output string.
|
||||
*
|
||||
* @param int len : the string length.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void send_packet(uint8_t *p, int len);
|
||||
|
||||
/**
|
||||
* @brief Receive an packet from download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *p : the pointer to input string.
|
||||
*
|
||||
* @param int len : If string length > len, the string will be truncated.
|
||||
*
|
||||
* @param uint8_t is_sync : 0, only one UART module;
|
||||
* 1, two UART modules.
|
||||
*
|
||||
* @return int : the length of the string.
|
||||
*/
|
||||
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
|
||||
|
||||
extern UartDevice UartDev;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_UART_H_ */
|
||||
Reference in New Issue
Block a user