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https://github.com/espressif/esp-idf.git
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change(esp_rom): optimize target-specific header files layout in components/esp_rom
This commit is contained in:
Xiaoyu Liu
41
components/esp_rom/esp32s3/include/esp32s3/rom/aes.h
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41
components/esp_rom/esp32s3/include/esp32s3/rom/aes.h
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@@ -0,0 +1,41 @@
|
||||
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum AES_TYPE {
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AES_ENC,
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AES_DEC,
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};
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enum AES_BITS {
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AES128,
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AES192,
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AES256
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};
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void ets_aes_enable(void);
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void ets_aes_disable(void);
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int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits);
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int ets_aes_setkey_enc(const void *key, enum AES_BITS bits);
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int ets_aes_setkey_dec(const void *key, enum AES_BITS bits);
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void ets_aes_block(const void *input, void *output);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,17 @@
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void));
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#ifdef __cplusplus
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}
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#endif
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32
components/esp_rom/esp32s3/include/esp32s3/rom/bigint.h
Normal file
32
components/esp_rom/esp32s3/include/esp32s3/rom/bigint.h
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@@ -0,0 +1,32 @@
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/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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void ets_bigint_enable(void);
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void ets_bigint_disable(void);
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int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words);
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int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words);
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int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words);
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void ets_bigint_wait_finish(void);
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int ets_bigint_getz(uint32_t *z, uint32_t len_words);
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#ifdef __cplusplus
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}
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#endif
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1199
components/esp_rom/esp32s3/include/esp32s3/rom/cache.h
Normal file
1199
components/esp_rom/esp32s3/include/esp32s3/rom/cache.h
Normal file
File diff suppressed because it is too large
Load Diff
114
components/esp_rom/esp32s3/include/esp32s3/rom/crc.h
Normal file
114
components/esp_rom/esp32s3/include/esp32s3/rom/crc.h
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@@ -0,0 +1,114 @@
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/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup crc_apis, uart configuration and communication related apis
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* @brief crc apis
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*/
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/** @addtogroup crc_apis
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* @{
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*/
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/* Standard CRC8/16/32 algorithms. */
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// CRC-8 x8+x2+x1+1 0x07
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// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
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// CRC32:
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//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
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//If your buf is not continuous, you can use the first result to be the second parameter.
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/**
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* @brief Crc32 value that is in little endian.
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*
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* @param uint32_t crc : init crc value, use 0 at the first use.
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*
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* @param uint8_t const *buf : buffer to start calculate crc.
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*
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* @param uint32_t len : buffer length in byte.
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*
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* @return None
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*/
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uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
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/**
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* @brief Crc32 value that is in big endian.
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*
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* @param uint32_t crc : init crc value, use 0 at the first use.
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*
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* @param uint8_t const *buf : buffer to start calculate crc.
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*
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* @param uint32_t len : buffer length in byte.
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*
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* @return None
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*/
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uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
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/**
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* @brief Crc16 value that is in little endian.
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*
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* @param uint16_t crc : init crc value, use 0 at the first use.
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*
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* @param uint8_t const *buf : buffer to start calculate crc.
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*
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* @param uint32_t len : buffer length in byte.
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*
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* @return None
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*/
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uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
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/**
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* @brief Crc16 value that is in big endian.
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*
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* @param uint16_t crc : init crc value, use 0 at the first use.
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*
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* @param uint8_t const *buf : buffer to start calculate crc.
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*
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* @param uint32_t len : buffer length in byte.
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*
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* @return None
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*/
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uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
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/**
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* @brief Crc8 value that is in little endian.
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*
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* @param uint8_t crc : init crc value, use 0 at the first use.
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*
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* @param uint8_t const *buf : buffer to start calculate crc.
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*
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* @param uint32_t len : buffer length in byte.
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*
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* @return None
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*/
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uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
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/**
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* @brief Crc8 value that is in big endian.
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*
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* @param uint32_t crc : init crc value, use 0 at the first use.
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*
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* @param uint8_t const *buf : buffer to start calculate crc.
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*
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* @param uint32_t len : buffer length in byte.
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*
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* @return None
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*/
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uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,134 @@
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/*
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||||
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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||||
* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#define ETS_DS_IV_LEN 16
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/* Length of parameter 'C' stored in flash */
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#define ETS_DS_C_LEN (12672 / 8)
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/* Encrypted ETS data. Recommended to store in flash in this format.
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*/
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typedef struct {
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/* RSA LENGTH register parameters
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* (number of words in RSA key & operands, minus one).
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*
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* Max value 127 (for RSA 4096).
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*
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* This value must match the length field encrypted and stored in 'c',
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* or invalid results will be returned. (The DS peripheral will
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* always use the value in 'c', not this value, so an attacker can't
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* alter the DS peripheral results this way, it will just truncate or
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* extend the message and the resulting signature in software.)
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*/
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unsigned rsa_length;
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/* IV value used to encrypt 'c' */
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uint8_t iv[ETS_DS_IV_LEN];
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/* Encrypted Digital Signature parameters. Result of AES-CBC encryption
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of plaintext values. Includes an encrypted message digest.
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*/
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uint8_t c[ETS_DS_C_LEN];
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} ets_ds_data_t;
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typedef enum {
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ETS_DS_OK,
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ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */
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ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */
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ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */
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ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */
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} ets_ds_result_t;
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void ets_ds_enable(void);
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void ets_ds_disable(void);
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/*
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* @brief Start signing a message (or padded message digest) using the Digital Signature peripheral
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*
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* - @param message Pointer to message (or padded digest) containing the message to sign. Should be
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* (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data
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* in flash.
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*
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* Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling
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* this function, and is responsible for calling ets_ds_finish_sign() and then
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* ets_hmac_invalidate_downstream() afterwards.
|
||||
*
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* @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid,
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* EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly.
|
||||
*/
|
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ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data);
|
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|
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|
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/*
|
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* @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign()
|
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*
|
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* A result of false indicates that a call to ets_ds_finish_sign() will not block.
|
||||
*
|
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* Only valid if ets_ds_enable() has been called.
|
||||
*/
|
||||
bool ets_ds_is_busy(void);
|
||||
|
||||
|
||||
/* @brief Finish signing a message using the Digital Signature peripheral
|
||||
*
|
||||
* Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until
|
||||
* peripheral is no longer busy.
|
||||
*
|
||||
* - @param signature Pointer to buffer to contain the signature. Should be
|
||||
* (data->rsa_length + 1)*4 bytes long.
|
||||
* - @param data Should match the 'data' parameter passed to ets_ds_start_sign()
|
||||
*
|
||||
* @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid,
|
||||
* ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the
|
||||
* encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a
|
||||
* digest is produced anyhow.)
|
||||
*/
|
||||
ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data);
|
||||
|
||||
|
||||
/* Plaintext parameters used by Digital Signature.
|
||||
|
||||
Not used for signing with DS peripheral, but can be encrypted
|
||||
in-device by calling ets_ds_encrypt_params()
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Y[4096 / 32];
|
||||
uint32_t M[4096 / 32];
|
||||
uint32_t Rb[4096 / 32];
|
||||
uint32_t M_prime;
|
||||
uint32_t length;
|
||||
} ets_ds_p_data_t;
|
||||
|
||||
typedef enum {
|
||||
ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */
|
||||
ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */
|
||||
} ets_ds_key_t;
|
||||
|
||||
/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral
|
||||
*
|
||||
* @param data Output buffer to store encrypted data, suitable for later use generating signatures.
|
||||
* @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
|
||||
* @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored.
|
||||
* @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased.
|
||||
* @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral)
|
||||
*
|
||||
* @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters.
|
||||
*/
|
||||
ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
345
components/esp_rom/esp32s3/include/esp32s3/rom/efuse.h
Normal file
345
components/esp_rom/esp32s3/include/esp32s3/rom/efuse.h
Normal file
@@ -0,0 +1,345 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/** \defgroup efuse_APIs efuse APIs
|
||||
* @brief ESP32 efuse read/write APIs
|
||||
* @attention
|
||||
*
|
||||
*/
|
||||
|
||||
/** @addtogroup efuse_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
ETS_EFUSE_KEY_PURPOSE_USER = 0,
|
||||
ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
|
||||
ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2,
|
||||
ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3,
|
||||
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
|
||||
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
|
||||
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
|
||||
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
|
||||
ETS_EFUSE_KEY_PURPOSE_MAX,
|
||||
} ets_efuse_purpose_t;
|
||||
|
||||
typedef enum {
|
||||
ETS_EFUSE_BLOCK0 = 0,
|
||||
ETS_EFUSE_MAC_SPI_SYS_0 = 1,
|
||||
ETS_EFUSE_BLOCK_SYS_DATA = 2,
|
||||
ETS_EFUSE_BLOCK_USR_DATA = 3,
|
||||
ETS_EFUSE_BLOCK_KEY0 = 4,
|
||||
ETS_EFUSE_BLOCK_KEY1 = 5,
|
||||
ETS_EFUSE_BLOCK_KEY2 = 6,
|
||||
ETS_EFUSE_BLOCK_KEY3 = 7,
|
||||
ETS_EFUSE_BLOCK_KEY4 = 8,
|
||||
ETS_EFUSE_BLOCK_KEY5 = 9,
|
||||
ETS_EFUSE_BLOCK_KEY6 = 10,
|
||||
ETS_EFUSE_BLOCK_MAX,
|
||||
} ets_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief set timing according the apb clock, so no read error or write error happens.
|
||||
*
|
||||
* @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M.
|
||||
*
|
||||
* @return : 0 if success, others if clock not accepted
|
||||
*/
|
||||
int ets_efuse_set_timing(uint32_t clock);
|
||||
|
||||
/**
|
||||
* @brief Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return : 0 if success, others if apb clock is not accepted
|
||||
*/
|
||||
int ets_efuse_read(void);
|
||||
|
||||
/**
|
||||
* @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
|
||||
*
|
||||
* @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
|
||||
*
|
||||
* @return : 0 if success, others if apb clock is not accepted
|
||||
*/
|
||||
int ets_efuse_program(ets_efuse_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Set all Efuse program registers to zero.
|
||||
*
|
||||
* Call this before writing new data to the program registers.
|
||||
*/
|
||||
void ets_efuse_clear_program_registers(void);
|
||||
|
||||
/**
|
||||
* @brief Program a block of key data to an efuse block
|
||||
*
|
||||
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
|
||||
* @param purpose Purpose to set for this key. Purpose must be already unset.
|
||||
* @param data Pointer to data to write.
|
||||
* @param data_len Length of data to write.
|
||||
*
|
||||
* @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
|
||||
*/
|
||||
int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
|
||||
|
||||
|
||||
/* @brief Return the address of a particular efuse block's first read register
|
||||
*
|
||||
* @param block Index of efuse block to look up
|
||||
*
|
||||
* @return 0 if block is invalid, otherwise a numeric read register address
|
||||
* of the first word in the block.
|
||||
*/
|
||||
uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Return the current purpose set for an efuse key block
|
||||
*
|
||||
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
|
||||
*/
|
||||
ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
|
||||
|
||||
/**
|
||||
* @brief Find a key block with the particular purpose set
|
||||
*
|
||||
* @param purpose Purpose to search for.
|
||||
* @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
|
||||
* @return true if found, false if not found. If false, value at key_block pointer is unchanged.
|
||||
*/
|
||||
bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
|
||||
|
||||
/**
|
||||
* Return true if the key block is unused, false otherwise.
|
||||
*
|
||||
* An unused key block is all zero content, not read or write protected,
|
||||
* and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
|
||||
*
|
||||
* @param key_block key block to check.
|
||||
*
|
||||
* @return true if key block is unused, false if key block or used
|
||||
* or the specified block index is not a key block.
|
||||
*/
|
||||
bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Search for an unused key block and return the first one found.
|
||||
*
|
||||
* See @ref ets_efuse_key_block_unused for a description of an unused key block.
|
||||
*
|
||||
* @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
|
||||
*/
|
||||
ets_efuse_block_t ets_efuse_find_unused_key_block(void);
|
||||
|
||||
/**
|
||||
* @brief Return the number of unused efuse key blocks (0-6)
|
||||
*/
|
||||
unsigned ets_efuse_count_unused_key_blocks(void);
|
||||
|
||||
/**
|
||||
* @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
|
||||
*
|
||||
* @param data Pointer to data buffer (length 32 bytes)
|
||||
* @param rs_values Pointer to write encoded data to (length 12 bytes)
|
||||
*/
|
||||
void ets_efuse_rs_calculate(const void *data, void *rs_values);
|
||||
|
||||
/**
|
||||
* @brief Read spi flash pads configuration from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0 for default SPI pins.
|
||||
* - 1 for default HSPI pins.
|
||||
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
|
||||
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
|
||||
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
|
||||
*/
|
||||
uint32_t ets_efuse_get_spiconfig(void);
|
||||
|
||||
/**
|
||||
* @brief Read spi flash wp pad from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0x3f for invalid.
|
||||
* - 0~46 is valid.
|
||||
*/
|
||||
uint32_t ets_efuse_get_wp_pad(void);
|
||||
|
||||
/**
|
||||
* @brief Read if download mode disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable download mode.
|
||||
* - false for efuse doesn't disable download mode.
|
||||
*/
|
||||
bool ets_efuse_download_modes_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if legacy spi flash boot mode disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable legacy spi flash boot mode.
|
||||
* - false for efuse doesn't disable legacy spi flash boot mode.
|
||||
*/
|
||||
bool ets_efuse_legacy_spi_boot_mode_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if uart print control value from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0 for uart force print.
|
||||
* - 1 for uart print when GPIO46 is low when digital reset.
|
||||
* 2 for uart print when GPIO46 is high when digital reset.
|
||||
* 3 for uart force silent
|
||||
*/
|
||||
uint32_t ets_efuse_get_uart_print_control(void);
|
||||
|
||||
/**
|
||||
* @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 1 for efuse disable USB-Serial-JTAG print during rom boot.
|
||||
* - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot.
|
||||
*/
|
||||
uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if usb download mode disabled from Efuse
|
||||
*
|
||||
* (Also returns true if security download mode is enabled, as this mode
|
||||
* disables USB download.)
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable usb download mode.
|
||||
* - false for efuse doesn't disable usb download mode.
|
||||
*/
|
||||
bool ets_efuse_usb_download_mode_disabled(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read if usb module disabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse disable usb module.
|
||||
* - false for efuse doesn't disable usb module.
|
||||
*/
|
||||
bool ets_efuse_usb_module_disabled(void);
|
||||
|
||||
/**
|
||||
* @brief Read if security download modes enabled from Efuse
|
||||
*
|
||||
* @return
|
||||
* - true for efuse enable security download mode.
|
||||
* - false for efuse doesn't enable security download mode.
|
||||
*/
|
||||
bool ets_efuse_security_download_modes_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if secure boot is enabled in EFuse
|
||||
*/
|
||||
bool ets_efuse_secure_boot_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if secure boot aggressive revoke is enabled in EFuse
|
||||
*/
|
||||
bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if cache encryption (flash, PSRAM, etc) is enabled from boot via EFuse
|
||||
*/
|
||||
bool ets_efuse_cache_encryption_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU
|
||||
*/
|
||||
bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void);
|
||||
|
||||
/**
|
||||
* @brief Return true if EFuse indicates to send a flash resume command.
|
||||
*/
|
||||
bool ets_efuse_force_send_resume(void);
|
||||
|
||||
/**
|
||||
* @brief return the time in us ROM boot need wait flash to power on from Efuse
|
||||
*
|
||||
* @return
|
||||
* - uint32_t the time in us.
|
||||
*/
|
||||
uint32_t ets_efuse_get_flash_delay_us(void);
|
||||
|
||||
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
|
||||
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
|
||||
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
|
||||
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
|
||||
|
||||
/**
|
||||
* @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
|
||||
* the JTAG_CTRL registers.
|
||||
*
|
||||
* Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
|
||||
*
|
||||
* Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
|
||||
*
|
||||
* @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
|
||||
* @param key_block Index of a key block containing the source for this key.
|
||||
*
|
||||
* @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
|
||||
*/
|
||||
int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
|
||||
|
||||
/**
|
||||
* @brief A crc8 algorithm used for MAC addresses in efuse
|
||||
*
|
||||
* @param unsigned char const *p : Pointer to original data.
|
||||
*
|
||||
* @param unsigned int len : Data length in byte.
|
||||
*
|
||||
* @return unsigned char: Crc value.
|
||||
*/
|
||||
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
566
components/esp_rom/esp32s3/include/esp32s3/rom/ets_sys.h
Normal file
566
components/esp_rom/esp32s3/include/esp32s3/rom/ets_sys.h
Normal file
@@ -0,0 +1,566 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup ets_sys_apis, ets system related apis
|
||||
* @brief ets system apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_sys_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* NOTE
|
||||
* Many functions in this header files can't be run in FreeRTOS.
|
||||
* Please see the comment of the Functions.
|
||||
* There are also some functions that doesn't work on FreeRTOS
|
||||
* without listed in the header, such as:
|
||||
* xtos functions start with "_xtos_" in ld file.
|
||||
*
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
/** \defgroup ets_apis, Espressif Task Scheduler related apis
|
||||
* @brief ets apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
ETS_OK = 0, /**< return successful in ets*/
|
||||
ETS_FAILED = 1, /**< return failed in ets*/
|
||||
ETS_PENDING = 2,
|
||||
ETS_BUSY = 3,
|
||||
ETS_CANCEL = 4,
|
||||
} ETS_STATUS;
|
||||
|
||||
typedef ETS_STATUS ets_status_t;
|
||||
|
||||
typedef uint32_t ETSSignal;
|
||||
typedef uint32_t ETSParam;
|
||||
|
||||
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
|
||||
|
||||
struct ETSEventTag {
|
||||
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
|
||||
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
|
||||
};
|
||||
|
||||
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/
|
||||
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_boot_apis, Boot routing related apis
|
||||
* @brief ets boot apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern const char *const exc_cause_table[40]; ///**< exception cause that defined by the core.*/
|
||||
|
||||
/**
|
||||
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
|
||||
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
|
||||
*
|
||||
* @param uint32_t start : the PRO Entry code address value in uint32_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_set_user_start(uint32_t start);
|
||||
|
||||
/**
|
||||
* @brief Set App cpu Entry code, code can be called in PRO CPU.
|
||||
* When APP booting is completed, APP CPU will call the Entry code if not NULL.
|
||||
*
|
||||
* @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_set_appcpu_boot_addr(uint32_t start);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
|
||||
* @brief ets printf apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_printf_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
|
||||
* Can not print float point data format, or longlong data format.
|
||||
* So we maybe only use this in ROM.
|
||||
*
|
||||
* @param const char *fmt : See printf.
|
||||
*
|
||||
* @param ... : See printf.
|
||||
*
|
||||
* @return int : the length printed to the output device.
|
||||
*/
|
||||
int ets_printf(const char *fmt, ...);
|
||||
|
||||
/**
|
||||
* @brief Get the uart channel of ets_printf(uart_tx_one_char).
|
||||
*
|
||||
* @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
|
||||
*/
|
||||
uint8_t ets_get_printf_channel(void);
|
||||
|
||||
/**
|
||||
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
|
||||
* Can not print float point data format, or longlong data format
|
||||
*
|
||||
* @param char c : char to output.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_write_char_uart(char c);
|
||||
|
||||
/**
|
||||
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
|
||||
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
|
||||
*
|
||||
* @param void (*)(char) p: Output function to install.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_putc1(void (*p)(char c));
|
||||
|
||||
/**
|
||||
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
|
||||
* To install putc2, which is defaulted installed as NULL.
|
||||
*
|
||||
* @param void (*)(char) p: Output function to install.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_putc2(void (*p)(char c));
|
||||
|
||||
/**
|
||||
* @brief Install putc1 as ets_write_char_uart.
|
||||
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_uart_printf(void);
|
||||
|
||||
#define ETS_PRINTF(...) ets_printf(...)
|
||||
|
||||
#define ETS_ASSERT(v) do { \
|
||||
if (!(v)) { \
|
||||
ets_printf("%s %u \n", __FILE__, __LINE__); \
|
||||
while (1) {}; \
|
||||
} \
|
||||
} while (0);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
|
||||
* @brief ets timer apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_timer_apis
|
||||
* @{
|
||||
*/
|
||||
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
|
||||
|
||||
typedef struct _ETSTIMER_ {
|
||||
struct _ETSTIMER_ *timer_next; /**< timer linker*/
|
||||
uint32_t timer_expire; /**< abstract time when timer expire*/
|
||||
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
|
||||
ETSTimerFunc *timer_func; /**< timer handler*/
|
||||
void *timer_arg; /**< timer handler argument*/
|
||||
} ETSTimer;
|
||||
|
||||
/**
|
||||
* @brief Init ets timer, this timer range is 640 us to 429496 ms
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_init(void);
|
||||
|
||||
/**
|
||||
* @brief In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_deinit(void);
|
||||
|
||||
/**
|
||||
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
|
||||
*
|
||||
* @param bool repeat : Timer is periodic repeated.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
|
||||
|
||||
/**
|
||||
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
|
||||
*
|
||||
* @param bool repeat : Timer is periodic repeated.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
|
||||
|
||||
/**
|
||||
* @brief Disarm an ets timer.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_disarm(ETSTimer *timer);
|
||||
|
||||
/**
|
||||
* @brief Set timer callback and argument.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param ETSTimerFunc *pfunction : Timer callback.
|
||||
*
|
||||
* @param void *parg : Timer callback argument.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
|
||||
|
||||
/**
|
||||
* @brief Unset timer callback and argument to NULL.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_done(ETSTimer *ptimer);
|
||||
|
||||
/**
|
||||
* @brief CPU do while loop for some time.
|
||||
* In FreeRTOS task, please call FreeRTOS apis.
|
||||
*
|
||||
* @param uint32_t us : Delay time in us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_delay_us(uint32_t us);
|
||||
|
||||
/**
|
||||
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
|
||||
* Call this function when CPU frequency is changed.
|
||||
*
|
||||
* @param uint32_t ticks_per_us : CPU ticks per us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_update_cpu_frequency(uint32_t ticks_per_us);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the real CPU ticks per us to the ets.
|
||||
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : CPU ticks per us record in ets.
|
||||
*/
|
||||
uint32_t ets_get_cpu_frequency(void);
|
||||
|
||||
/**
|
||||
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : if stored in efuse(not 0)
|
||||
* clock = ets_efuse_get_xtal_freq() * 1000000;
|
||||
* else if analog_8M in efuse
|
||||
* clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock();
|
||||
* else clock = 40M.
|
||||
*/
|
||||
uint32_t ets_get_xtal_freq(void);
|
||||
|
||||
/**
|
||||
* @brief Get the apb divisor. The xtal frequency gets divided
|
||||
* by this value to generate the APB clock.
|
||||
* When any types of reset happens, the default value is 2.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : 1 or 2.
|
||||
*/
|
||||
uint32_t ets_get_xtal_div(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Modifies the apb divisor. The xtal frequency gets divided by this to
|
||||
* generate the APB clock.
|
||||
*
|
||||
* @note The xtal frequency divisor is 2 by default as the glitch detector
|
||||
* doesn't properly stop glitches when it is 1. Please do not set the
|
||||
* divisor to 1 before the PLL is active without being aware that you
|
||||
* may be introducing a security risk.
|
||||
*
|
||||
* @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq.
|
||||
*/
|
||||
void ets_set_xtal_div(int div);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get apb_freq value, If value not stored in RTC_STORE5, than store.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
|
||||
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
|
||||
* else store ets_get_detected_xtal_freq() in.
|
||||
*/
|
||||
uint32_t ets_get_apb_freq(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_intr_apis, ets interrupt configure related apis
|
||||
* @brief ets intr apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_intr_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
|
||||
|
||||
/**
|
||||
* @brief Attach a interrupt handler to a CPU interrupt number.
|
||||
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param int i : CPU interrupt number.
|
||||
*
|
||||
* @param ets_isr_t func : Interrupt handler.
|
||||
*
|
||||
* @param void *arg : argument of the handler.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_attach(int i, ets_isr_t func, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Mask the interrupts which show in mask bits.
|
||||
* This function equals to _xtos_ints_off(mask).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_mask(uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Unmask the interrupts which show in mask bits.
|
||||
* This function equals to _xtos_ints_on(mask).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_unmask(uint32_t unmask);
|
||||
|
||||
/**
|
||||
* @brief Lock the interrupt to level 2.
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_intr_lock(void);
|
||||
|
||||
/**
|
||||
* @brief Unlock the interrupt to level 0.
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_intr_unlock(void);
|
||||
|
||||
/**
|
||||
* @brief Attach an CPU interrupt to a hardware source.
|
||||
* We have 4 steps to use an interrupt:
|
||||
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
|
||||
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
|
||||
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
|
||||
* 4.Enable interrupt in the module.
|
||||
*
|
||||
* @param int cpu_no : The CPU which the interrupt number belongs.
|
||||
*
|
||||
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
|
||||
*
|
||||
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
|
||||
#define _ETSTR(v) # v
|
||||
#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
|
||||
__asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \
|
||||
: "=a" (__tmp) : : "memory" ); \
|
||||
})
|
||||
|
||||
#ifdef CONFIG_NONE_OS
|
||||
#define ETS_INTR_LOCK() \
|
||||
ets_intr_lock()
|
||||
|
||||
#define ETS_INTR_UNLOCK() \
|
||||
ets_intr_unlock()
|
||||
|
||||
#define ETS_ISR_ATTACH \
|
||||
ets_isr_attach
|
||||
|
||||
#define ETS_INTR_ENABLE(inum) \
|
||||
ets_isr_unmask((1<<inum))
|
||||
|
||||
#define ETS_INTR_DISABLE(inum) \
|
||||
ets_isr_mask((1<<inum))
|
||||
|
||||
#define ETS_WMAC_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_GPIO_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_UART0_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_WDT_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_SLC_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_BB_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_BB_INUM)
|
||||
|
||||
#define ETS_BB_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_BB_INUM)
|
||||
|
||||
#define ETS_UART0_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_UART0_INUM)
|
||||
|
||||
#define ETS_UART0_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_UART0_INUM)
|
||||
|
||||
#define ETS_GPIO_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_GPIO_INUM)
|
||||
|
||||
#define ETS_GPIO_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_GPIO_INUM)
|
||||
|
||||
#define ETS_WDT_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_WDT_INUM)
|
||||
|
||||
#define ETS_WDT_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_WDT_INUM)
|
||||
|
||||
#define ETS_TG0_T0_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
|
||||
|
||||
#define ETS_TG0_T0_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
|
||||
|
||||
#define ETS_SLC_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_SLC_INUM)
|
||||
|
||||
#define ETS_SLC_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_SLC_INUM)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifndef MAC2STR
|
||||
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
|
||||
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#endif
|
||||
|
||||
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
|
||||
|
||||
#ifdef ESP_PLATFORM
|
||||
// Remove in IDF v6.0 (IDF-7044)
|
||||
typedef enum {
|
||||
OK = 0,
|
||||
FAIL,
|
||||
PENDING,
|
||||
BUSY,
|
||||
CANCEL,
|
||||
} STATUS __attribute__((deprecated("Use ETS_STATUS instead")));
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
210
components/esp_rom/esp32s3/include/esp32s3/rom/gpio.h
Normal file
210
components/esp_rom/esp32s3/include/esp32s3/rom/gpio.h
Normal file
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/gpio_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup gpio_apis, uart configuration and communication related apis
|
||||
* @brief gpio apis
|
||||
*/
|
||||
|
||||
/** @addtogroup gpio_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
|
||||
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
|
||||
#define GPIO_ID_PIN0 0
|
||||
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
|
||||
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
|
||||
|
||||
#define GPIO_FUNC_IN_HIGH 0x38
|
||||
#define GPIO_FUNC_IN_LOW 0x3C
|
||||
|
||||
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
|
||||
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
|
||||
|
||||
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
|
||||
|
||||
typedef enum {
|
||||
GPIO_PIN_INTR_DISABLE = 0,
|
||||
GPIO_PIN_INTR_POSEDGE = 1,
|
||||
GPIO_PIN_INTR_NEGEDGE = 2,
|
||||
GPIO_PIN_INTR_ANYEDGE = 3,
|
||||
GPIO_PIN_INTR_LOLEVEL = 4,
|
||||
GPIO_PIN_INTR_HILEVEL = 5
|
||||
} GPIO_INT_TYPE;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
|
||||
* There is no particular ordering guaranteed; so if the order of writes is significant,
|
||||
* calling code should divide a single call into multiple calls.
|
||||
*
|
||||
* @param uint32_t set_mask : the gpios that need high level.
|
||||
*
|
||||
* @param uint32_t clear_mask : the gpios that need low level.
|
||||
*
|
||||
* @param uint32_t enable_mask : the gpios that need be changed.
|
||||
*
|
||||
* @param uint32_t disable_mask : the gpios that need disable output.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
|
||||
*/
|
||||
uint32_t gpio_input_get(void);
|
||||
|
||||
/**
|
||||
* @brief Set GPIO to wakeup the ESP32.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t i: gpio number.
|
||||
*
|
||||
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
|
||||
|
||||
/**
|
||||
* @brief disable GPIOs to wakeup the ESP32.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pin_wakeup_disable(void);
|
||||
|
||||
/**
|
||||
* @brief set gpio input to a signal, one gpio can input to several signals.
|
||||
*
|
||||
* @param uint32_t gpio : gpio number, 0~0x2f
|
||||
* gpio == 0x3C, input 0 to signal
|
||||
* gpio == 0x3A, input nothing to signal
|
||||
* gpio == 0x38, input 1 to signal
|
||||
*
|
||||
* @param uint32_t signal_idx : signal index.
|
||||
*
|
||||
* @param bool inv : the signal is inv or not
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
|
||||
|
||||
/**
|
||||
* @brief set signal output to gpio, one signal can output to several gpios.
|
||||
*
|
||||
* @param uint32_t gpio : gpio number, 0~0x2f
|
||||
*
|
||||
* @param uint32_t signal_idx : signal index.
|
||||
* signal_idx == 0x100, cancel output put to the gpio
|
||||
*
|
||||
* @param bool out_inv : the signal output is invert or not
|
||||
*
|
||||
* @param bool oen_inv : the signal output enable is invert or not
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
|
||||
|
||||
/**
|
||||
* @brief Select pad as a gpio function from IOMUX.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_select_gpio(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Set pad driver capability.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @param uint32_t drv : 0-3
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
|
||||
|
||||
/**
|
||||
* @brief Pull up the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_pullup(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Pull down the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_pulldown(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Unhold the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_unhold(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Hold the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_hold(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief enable gpio pad input.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_input_enable(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief disable gpio pad input.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x2f
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_input_disable(uint32_t gpio_num);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
51
components/esp_rom/esp32s3/include/esp32s3/rom/hmac.h
Normal file
51
components/esp_rom/esp32s3/include/esp32s3/rom/hmac.h
Normal file
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include "efuse.h"
|
||||
|
||||
void ets_hmac_enable(void);
|
||||
|
||||
void ets_hmac_disable(void);
|
||||
|
||||
/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP)
|
||||
to digest a message.
|
||||
*/
|
||||
int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac);
|
||||
|
||||
/* Calculate a downstream HMAC message to temporarily enable JTAG, or
|
||||
to generate a Digital Signature data decryption key.
|
||||
|
||||
- purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
|
||||
or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
|
||||
|
||||
- key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6.
|
||||
This efuse block must have the corresponding purpose set in "purpose", or
|
||||
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL.
|
||||
|
||||
The result of this HMAC calculation is only made available "downstream" to the
|
||||
corresponding hardware module, and cannot be accessed by software.
|
||||
*/
|
||||
int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose);
|
||||
|
||||
/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream().
|
||||
*
|
||||
* - purpose must match a previous call to ets_hmac_calculate_downstream().
|
||||
*
|
||||
* After this function is called, the corresponding internal operation (JTAG or DS) will no longer
|
||||
* have access to the generated key.
|
||||
*/
|
||||
int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
85
components/esp_rom/esp32s3/include/esp32s3/rom/libc_stubs.h
Normal file
85
components/esp_rom/esp32s3/include/esp32s3/rom/libc_stubs.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <sys/lock.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <time.h>
|
||||
#include <reent.h>
|
||||
#include <errno.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ESP32-S3 ROM code contains implementations of some of C library functions.
|
||||
* Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
|
||||
* implementation defined in the following struct.
|
||||
*
|
||||
* The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
|
||||
* `syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
|
||||
* and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
|
||||
*
|
||||
* So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
|
||||
* application must allocate syscall table structure for each CPU being used, and populate it with pointers
|
||||
* to actual implementations of corresponding syscalls.
|
||||
*
|
||||
*/
|
||||
struct syscall_stub_table
|
||||
{
|
||||
struct _reent* (*__getreent)(void);
|
||||
void* (*_malloc_r)(struct _reent *r, size_t);
|
||||
void (*_free_r)(struct _reent *r, void*);
|
||||
void* (*_realloc_r)(struct _reent *r, void*, size_t);
|
||||
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
|
||||
void (*_abort)(void);
|
||||
int (*_system_r)(struct _reent *r, const char*);
|
||||
int (*_rename_r)(struct _reent *r, const char*, const char*);
|
||||
clock_t (*_times_r)(struct _reent *r, struct tms *);
|
||||
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
|
||||
void (*_raise_r)(struct _reent *r);
|
||||
int (*_unlink_r)(struct _reent *r, const char*);
|
||||
int (*_link_r)(struct _reent *r, const char*, const char*);
|
||||
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
|
||||
int (*_fstat_r)(struct _reent *r, int, struct stat *);
|
||||
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
|
||||
int (*_getpid_r)(struct _reent *r);
|
||||
int (*_kill_r)(struct _reent *r, int, int);
|
||||
void (*_exit_r)(struct _reent *r, int);
|
||||
int (*_close_r)(struct _reent *r, int);
|
||||
int (*_open_r)(struct _reent *r, const char *, int, int);
|
||||
int (*_write_r)(struct _reent *r, int, const void *, int);
|
||||
int (*_lseek_r)(struct _reent *r, int, int, int);
|
||||
int (*_read_r)(struct _reent *r, int, void *, int);
|
||||
void (*_retarget_lock_init)(_LOCK_T *lock);
|
||||
void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
|
||||
void (*_retarget_lock_close)(_LOCK_T lock);
|
||||
void (*_retarget_lock_close_recursive)(_LOCK_T lock);
|
||||
void (*_retarget_lock_acquire)(_LOCK_T lock);
|
||||
void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
|
||||
int (*_retarget_lock_try_acquire)(_LOCK_T lock);
|
||||
int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
|
||||
void (*_retarget_lock_release)(_LOCK_T lock);
|
||||
void (*_retarget_lock_release_recursive)(_LOCK_T lock);
|
||||
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap);
|
||||
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
|
||||
void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((__noreturn__));
|
||||
void (*__sinit) (struct _reent *r);
|
||||
void (*_cleanup_r) (struct _reent* r);
|
||||
};
|
||||
|
||||
extern struct syscall_stub_table *syscall_table_ptr;
|
||||
#define syscall_table_ptr_pro syscall_table_ptr
|
||||
#define syscall_table_ptr_app syscall_table_ptr
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
128
components/esp_rom/esp32s3/include/esp32s3/rom/lldesc.h
Normal file
128
components/esp_rom/esp32s3/include/esp32s3/rom/lldesc.h
Normal file
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "sys/queue.h"
|
||||
#include "esp_rom_lldesc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LLDESC_TX_MBLK_SIZE 268 /* */
|
||||
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
|
||||
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
|
||||
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
|
||||
#ifdef ESP_MAC_5
|
||||
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
|
||||
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
|
||||
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
|
||||
#else
|
||||
#ifdef SBUF_RXTX
|
||||
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
|
||||
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
|
||||
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
|
||||
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
|
||||
#endif
|
||||
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
|
||||
|
||||
#ifdef IEEE80211_RX_AMPDU
|
||||
#define LLDESC_RX_MBLK_NUM 30
|
||||
#else
|
||||
#define LLDESC_RX_MBLK_NUM 10
|
||||
#endif /*IEEE80211_RX_AMPDU*/
|
||||
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
|
||||
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
|
||||
#endif /* !ESP_MAC_5 */
|
||||
typedef struct tx_ampdu_entry_s {
|
||||
uint32_t sub_len : 12,
|
||||
dili_num : 7,
|
||||
: 1,
|
||||
null_byte: 2,
|
||||
data : 1,
|
||||
enc : 1,
|
||||
seq : 8;
|
||||
} tx_ampdu_entry_t;
|
||||
|
||||
typedef struct lldesc_chain_s {
|
||||
lldesc_t *head;
|
||||
lldesc_t *tail;
|
||||
} lldesc_chain_t;
|
||||
|
||||
#ifdef SBUF_RXTX
|
||||
enum sbuf_mask_s {
|
||||
SBUF_MOVE_NO = 0,
|
||||
SBUF_MOVE_TX2RX,
|
||||
SBUF_MOVE_RX2TX,
|
||||
} ;
|
||||
|
||||
#define SBUF_MOVE_STEP 8
|
||||
#endif
|
||||
#define LLDESC_SIZE sizeof(struct lldesc_s)
|
||||
|
||||
/* SLC Descriptor */
|
||||
#define LLDESC_OWNER_MASK 0x80000000
|
||||
#define LLDESC_OWNER_SHIFT 31
|
||||
#define LLDESC_SW_OWNED 0
|
||||
#define LLDESC_HW_OWNED 1
|
||||
|
||||
#define LLDESC_EOF_MASK 0x40000000
|
||||
#define LLDESC_EOF_SHIFT 30
|
||||
|
||||
#define LLDESC_SOSF_MASK 0x20000000
|
||||
#define LLDESC_SOSF_SHIFT 29
|
||||
|
||||
#define LLDESC_LENGTH_MASK 0x00fff000
|
||||
#define LLDESC_LENGTH_SHIFT 12
|
||||
|
||||
#define LLDESC_SIZE_MASK 0x00000fff
|
||||
#define LLDESC_SIZE_SHIFT 0
|
||||
|
||||
#define LLDESC_ADDR_MASK 0x000fffff
|
||||
|
||||
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
|
||||
{
|
||||
lldesc_t *ds = head;
|
||||
uint32_t len = 0;
|
||||
|
||||
while (ds) {
|
||||
len += ds->length;
|
||||
ds = STAILQ_NEXT(ds, qe);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
|
||||
{
|
||||
ds->owner = owner;
|
||||
ds->eof = eof;
|
||||
ds->sosf = sosf;
|
||||
ds->length = len;
|
||||
}
|
||||
|
||||
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) \
|
||||
do { \
|
||||
(_desc)->owner = (_owner); \
|
||||
(_desc)->eof = (_eof); \
|
||||
(_desc)->sosf = (_sosf); \
|
||||
(_desc)->length = (_len); \
|
||||
} while(0)
|
||||
|
||||
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
|
||||
|
||||
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
|
||||
|
||||
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
40
components/esp_rom/esp32s3/include/esp32s3/rom/md5_hash.h
Normal file
40
components/esp_rom/esp32s3/include/esp32s3/rom/md5_hash.h
Normal file
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2003-2005, Jouni Malinen <j@w1.fi>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* MD5 internal definitions
|
||||
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of BSD
|
||||
* license.
|
||||
*
|
||||
* See README and COPYING for more details.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct MD5Context {
|
||||
uint32_t buf[4];
|
||||
uint32_t bits[2];
|
||||
uint8_t in[64];
|
||||
};
|
||||
|
||||
void MD5Init(struct MD5Context *context);
|
||||
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
|
||||
void MD5Final(unsigned char digest[16], struct MD5Context *context);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
323
components/esp_rom/esp32s3/include/esp32s3/rom/opi_flash.h
Normal file
323
components/esp_rom/esp32s3/include/esp32s3/rom/opi_flash.h
Normal file
@@ -0,0 +1,323 @@
|
||||
/*
|
||||
* copyright (c) Espressif System 2019
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ROM_OPI_FLASH_H_
|
||||
#define _ROM_OPI_FLASH_H_
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "spi_flash.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint8_t mode;
|
||||
uint8_t cmd_bit_len;
|
||||
uint16_t cmd;
|
||||
uint32_t addr;
|
||||
uint8_t addr_bit_len;
|
||||
uint8_t dummy_bit_len;
|
||||
uint8_t data_bit_len;
|
||||
uint8_t cs_sel: 4;
|
||||
uint8_t is_pe: 4;
|
||||
} esp_rom_opiflash_cmd_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t addr_bit_len;
|
||||
uint8_t dummy_bit_len;
|
||||
uint16_t cmd;
|
||||
uint8_t cmd_bit_len;
|
||||
uint8_t var_dummy_en;
|
||||
} esp_rom_opiflash_spi0rd_t;
|
||||
|
||||
typedef struct {
|
||||
esp_rom_opiflash_cmd_t rdid;
|
||||
esp_rom_opiflash_cmd_t rdsr;
|
||||
esp_rom_opiflash_cmd_t wren;
|
||||
esp_rom_opiflash_cmd_t se;
|
||||
esp_rom_opiflash_cmd_t be64k;
|
||||
esp_rom_opiflash_cmd_t read;
|
||||
esp_rom_opiflash_cmd_t pp;
|
||||
esp_rom_opiflash_spi0rd_t cache_rd_cmd;
|
||||
} esp_rom_opiflash_def_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t cmd; /*!< Command value */
|
||||
uint16_t cmdBitLen; /*!< Command byte length*/
|
||||
uint32_t *addr; /*!< Point to address value*/
|
||||
uint32_t addrBitLen; /*!< Address byte length*/
|
||||
uint32_t *txData; /*!< Point to send data buffer*/
|
||||
uint32_t txDataBitLen; /*!< Send data byte length.*/
|
||||
uint32_t *rxData; /*!< Point to receive data buffer*/
|
||||
uint32_t rxDataBitLen; /*!< Receive Data byte length.*/
|
||||
uint32_t dummyBitLen;
|
||||
} esp_rom_spi_cmd_t;
|
||||
|
||||
#define ESP_ROM_OPIFLASH_MUX_TAKE()
|
||||
#define ESP_ROM_OPIFLASH_MUX_GIVE()
|
||||
#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
|
||||
#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
|
||||
|
||||
// Definition of MX25UM25645G Octa Flash
|
||||
// SPI status register
|
||||
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
|
||||
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
|
||||
#define ESP_ROM_SPIFLASH_BP0 BIT2
|
||||
#define ESP_ROM_SPIFLASH_BP1 BIT3
|
||||
#define ESP_ROM_SPIFLASH_BP2 BIT4
|
||||
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
|
||||
#define ESP_ROM_SPIFLASH_QE BIT9
|
||||
|
||||
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
|
||||
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
|
||||
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
|
||||
#define ESP_ROM_FLASH_PAGE_SIZE 256
|
||||
|
||||
// FLASH commands
|
||||
#define ROM_FLASH_CMD_RDID 0x9F
|
||||
#define ROM_FLASH_CMD_WRSR 0x01
|
||||
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_WREN 0x06
|
||||
#define ROM_FLASH_CMD_WRDI 0x04
|
||||
#define ROM_FLASH_CMD_RDSR 0x05
|
||||
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_ERASE_SEC 0x20
|
||||
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
|
||||
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
|
||||
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_RSTEN 0x66
|
||||
#define ROM_FLASH_CMD_RST 0x99
|
||||
|
||||
#define ROM_FLASH_CMD_SE4B 0x21
|
||||
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
|
||||
#define ROM_FLASH_CMD_BE4B 0xDC
|
||||
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
|
||||
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
|
||||
#define ROM_FLASH_CMD_RST_OCT 0x6699
|
||||
|
||||
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
|
||||
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
|
||||
#define ROM_FLASH_CMD_FSTRD4B 0x0C
|
||||
#define ROM_FLASH_CMD_PP4B 0x12
|
||||
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
|
||||
|
||||
#define ROM_FLASH_CMD_RDID_OCT 0x609F
|
||||
#define ROM_FLASH_CMD_WREN_OCT 0xF906
|
||||
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
|
||||
#define ROM_FLASH_CMD_RDCR2 0x71
|
||||
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
|
||||
#define ROM_FLASH_CMD_WRCR2 0x72
|
||||
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
|
||||
|
||||
// Definitions for GigaDevice GD25LX256E Flash
|
||||
#define ROM_FLASH_CMD_RDFSR_GD 0x70
|
||||
#define ROM_FLASH_CMD_RD_GD 0x03
|
||||
#define ROM_FLASH_CMD_RD4B_GD 0x13
|
||||
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
|
||||
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
|
||||
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
|
||||
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
|
||||
|
||||
#define ROM_FLASH_CMD_PP_GD 0x02
|
||||
#define ROM_FLASH_CMD_PP4B_GD 0x12
|
||||
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
|
||||
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
|
||||
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
|
||||
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
|
||||
|
||||
#define ROM_FLASH_CMD_SE_GD 0x20
|
||||
#define ROM_FLASH_CMD_SE4B_GD 0x21
|
||||
#define ROM_FLASH_CMD_BE32K_GD 0x52
|
||||
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
|
||||
#define ROM_FLASH_CMD_BE64K_GD 0xD8
|
||||
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
|
||||
|
||||
#define ROM_FLASH_CMD_EN4B_GD 0xB7
|
||||
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
|
||||
|
||||
extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def;
|
||||
|
||||
/**
|
||||
* @brief init legacy driver for Octal Flash
|
||||
*/
|
||||
void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def);
|
||||
|
||||
// spi user mode command config
|
||||
/**
|
||||
* @brief Config the spi user command
|
||||
* @param spi_num spi port
|
||||
* @param pcmd pointer to accept the spi command struct
|
||||
*/
|
||||
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
|
||||
|
||||
/**
|
||||
* @brief Start a spi user command sequence
|
||||
* @param spi_num spi port
|
||||
* @param rx_buf buffer pointer to receive data
|
||||
* @param rx_len receive data length in byte
|
||||
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
|
||||
* @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
|
||||
*/
|
||||
void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
|
||||
|
||||
/**
|
||||
* @brief Config opi flash pads according to efuse settings.
|
||||
*/
|
||||
void esp_rom_opiflash_pin_config(void);
|
||||
|
||||
// set SPI read/write mode
|
||||
/**
|
||||
* @brief Set SPI operation mode
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Read Mode
|
||||
*/
|
||||
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Set data swap mode in DTR(DDR) mode
|
||||
* @param spi_num spi port
|
||||
* @param wr_swap to decide whether to swap fifo data in dtr write operation
|
||||
* @param rd_swap to decide whether to swap fifo data in dtr read operation
|
||||
*/
|
||||
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
|
||||
|
||||
|
||||
/**
|
||||
* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
*/
|
||||
void esp_rom_opiflash_mode_reset(int spi_num);
|
||||
|
||||
/**
|
||||
* @brief To execute a flash operation command
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Read Mode
|
||||
* @param cmd data to send in command field
|
||||
* @param cmd_bit_len bit length of command field
|
||||
* @param addr data to send in address field
|
||||
* @param addr_bit_len bit length of address field
|
||||
* @param dummy_bits bit length of dummy field
|
||||
* @param mosi_data data buffer to be sent in mosi field
|
||||
* @param mosi_bit_len bit length of data buffer to be sent in mosi field
|
||||
* @param miso_data data buffer to accept data in miso field
|
||||
* @param miso_bit_len bit length of data buffer to accept data in miso field
|
||||
* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
|
||||
* @param is_write_erase_operation to indicate whether this a write or erase flash operation
|
||||
*/
|
||||
void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t* mosi_data, int mosi_bit_len,
|
||||
uint8_t* miso_data, int miso_bit_len,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation);
|
||||
|
||||
/**
|
||||
* @brief send reset command to opi flash
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
*/
|
||||
void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
|
||||
/**
|
||||
* @brief to read opi flash ID
|
||||
* @note command format would be defined in initialization
|
||||
* @param[out] out_id buffer to accept id
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id);
|
||||
|
||||
/**
|
||||
* @brief to read opi flash status register
|
||||
* @note command format would be defined in initialization
|
||||
* @return opi flash status value
|
||||
*/
|
||||
uint8_t esp_rom_opiflash_rdsr(void);
|
||||
|
||||
/**
|
||||
* @brief wait opi flash status register to be idle
|
||||
* @note command format would be defined in initialization
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void);
|
||||
|
||||
/**
|
||||
* @brief to erase flash sector
|
||||
* @note command format would be defined in initialization
|
||||
* @param sector_num the sector to be erased
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num);
|
||||
|
||||
/**
|
||||
* @brief to erase flash block
|
||||
* @note command format would be defined in initialization
|
||||
* @param block_num the block to be erased
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num);
|
||||
|
||||
/**
|
||||
* @brief to erase a flash area define by start address and length
|
||||
* @note command format would be defined in initialization
|
||||
* @param start_addr the start address to be erased
|
||||
* @param area_len the erea length to be erased
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len);
|
||||
|
||||
/**
|
||||
* @brief to read data from opi flash
|
||||
* @note command format would be defined in initialization
|
||||
* @param flash_addr flash address to read data from
|
||||
* @param data_addr data buffer to accept the data
|
||||
* @param len data length to be read
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len);
|
||||
|
||||
/**
|
||||
* @brief to write data to opi flash
|
||||
* @note command format would be defined in initialization
|
||||
* @param flash_addr flash address to write data to
|
||||
* @param data_addr data buffer to write to flash
|
||||
* @param len data length to write
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, const uint32_t *data_addr, int len);
|
||||
|
||||
/**
|
||||
* @brief send WREN command
|
||||
* @note command format would be defined in initialization
|
||||
* @param arg not used, set to NULL
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_wren(void* arg);
|
||||
|
||||
/**
|
||||
* @brief to configure SPI0 read flash command format for cache
|
||||
* @note command format would be defined in initialization
|
||||
*
|
||||
*/
|
||||
void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache);
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, uint8_t* buf, int len);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
90
components/esp_rom/esp32s3/include/esp32s3/rom/rom_layout.h
Normal file
90
components/esp_rom/esp32s3/include/esp32s3/rom/rom_layout.h
Normal file
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SUPPORT_WIFI 1
|
||||
#define SUPPORT_BTDM 1
|
||||
#define SUPPORT_USB_DWCOTG 1
|
||||
|
||||
/* Structure and functions for returning ROM global layout
|
||||
*
|
||||
* This is for address symbols defined in the linker script, which may change during ECOs.
|
||||
*/
|
||||
typedef struct {
|
||||
void *dram0_stack_shared_mem_start;
|
||||
void *dram0_rtos_reserved_start;
|
||||
void *stack_sentry;
|
||||
void *stack;
|
||||
void *stack_sentry_app;
|
||||
void *stack_app;
|
||||
|
||||
/* BTDM data */
|
||||
#if SUPPORT_BTDM
|
||||
void *data_start_btdm;
|
||||
void *data_end_btdm;
|
||||
void *bss_start_btdm;
|
||||
void *bss_end_btdm;
|
||||
void *data_start_btdm_rom;
|
||||
void *data_end_btdm_rom;
|
||||
void *data_start_interface_btdm;
|
||||
void *data_end_interface_btdm;
|
||||
void *bss_start_interface_btdm;
|
||||
void *bss_end_interface_btdm;
|
||||
#endif
|
||||
|
||||
/* Other DRAM ranges */
|
||||
#if SUPPORT_BTDM || SUPPORT_WIFI
|
||||
void *dram_start_phyrom;
|
||||
void *dram_end_phyrom;
|
||||
#endif
|
||||
|
||||
#if SUPPORT_WIFI
|
||||
void *dram_start_coexist;
|
||||
void *dram_end_coexist;
|
||||
void *dram_start_net80211;
|
||||
void *dram_end_net80211;
|
||||
void *dram_start_pp;
|
||||
void *dram_end_pp;
|
||||
void *data_start_interface_coexist;
|
||||
void *data_end_interface_coexist;
|
||||
void *bss_start_interface_coexist;
|
||||
void *bss_end_interface_coexist;
|
||||
void *data_start_interface_net80211;
|
||||
void *data_end_interface_net80211;
|
||||
void *bss_start_interface_net80211;
|
||||
void *bss_end_interface_net80211;
|
||||
void *data_start_interface_pp;
|
||||
void *data_end_interface_pp;
|
||||
void *bss_start_interface_pp;
|
||||
void *bss_end_interface_pp;
|
||||
#endif
|
||||
|
||||
#if SUPPORT_USB_DWCOTG
|
||||
void *dram_start_usb_dwcotg_rom;
|
||||
void *dram_end_usb_dwcotg_rom;
|
||||
#else
|
||||
//Two reserved members are defined here, so the structure will not be broken,
|
||||
//please keep in mind that there is no memory can be released between
|
||||
//dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom.
|
||||
void *dram_start_usb_reserved_rom;
|
||||
void *dram_end_usb_reserved_rom;
|
||||
#endif
|
||||
|
||||
void *dram_start_uart_rom;
|
||||
void *dram_end_uart_rom;
|
||||
} ets_rom_layout_t;
|
||||
|
||||
extern const ets_rom_layout_t * const ets_rom_layout_p;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
35
components/esp_rom/esp32s3/include/esp32s3/rom/rsa_pss.h
Normal file
35
components/esp_rom/esp32s3/include/esp32s3/rom/rsa_pss.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ETS_SIG_LEN 384 /* Bytes */
|
||||
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
|
||||
|
||||
typedef struct {
|
||||
uint8_t n[384]; /* Public key modulus */
|
||||
uint32_t e; /* Public key exponent */
|
||||
uint8_t rinv[384];
|
||||
uint32_t mdash;
|
||||
} ets_rsa_pubkey_t;
|
||||
|
||||
bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
|
||||
|
||||
void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
|
||||
|
||||
bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
250
components/esp_rom/esp32s3/include/esp32s3/rom/rtc.h
Normal file
250
components/esp_rom/esp32s3/include/esp32s3/rom/rtc.h
Normal file
@@ -0,0 +1,250 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "esp_assert.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/reset_reasons.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup rtc_apis, rtc registers and memory related apis
|
||||
* @brief rtc apis
|
||||
*/
|
||||
|
||||
/** @addtogroup rtc_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**************************************************************************************
|
||||
* Note: *
|
||||
* Some Rtc memory and registers are used, in ROM or in internal library. *
|
||||
* Please do not use reserved or used rtc memory or registers. *
|
||||
* *
|
||||
*************************************************************************************
|
||||
* RTC Memory & Store Register usage
|
||||
*************************************************************************************
|
||||
* rtc memory addr type size usage
|
||||
* 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
|
||||
* 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
|
||||
*
|
||||
* 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
|
||||
*
|
||||
*************************************************************************************
|
||||
* RTC store registers usage
|
||||
* RTC_CNTL_STORE0_REG Reserved
|
||||
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
|
||||
* RTC_CNTL_STORE2_REG Boot time, low word
|
||||
* RTC_CNTL_STORE3_REG Boot time, high word
|
||||
* RTC_CNTL_STORE4_REG External XTAL frequency
|
||||
* RTC_CNTL_STORE5_REG FAST_RTC_MEMORY_LENGTH
|
||||
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
|
||||
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
|
||||
*************************************************************************************
|
||||
*/
|
||||
|
||||
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
|
||||
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
|
||||
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
|
||||
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
|
||||
#define RTC_ENTRY_LENGTH_REG RTC_CNTL_STORE5_REG
|
||||
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
|
||||
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
|
||||
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
|
||||
|
||||
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
|
||||
|
||||
typedef enum {
|
||||
AWAKE = 0, //<CPU ON
|
||||
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
|
||||
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
|
||||
} SLEEP_MODE;
|
||||
|
||||
typedef enum {
|
||||
NO_MEAN = 0,
|
||||
POWERON_RESET = 1, /**<1, Vbat power on reset*/
|
||||
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
|
||||
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
|
||||
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
|
||||
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
|
||||
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
|
||||
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
|
||||
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
|
||||
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
|
||||
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
|
||||
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
|
||||
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
|
||||
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
|
||||
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
|
||||
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
|
||||
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
|
||||
} RESET_REASON;
|
||||
|
||||
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
|
||||
|
||||
typedef enum {
|
||||
NO_SLEEP = 0,
|
||||
EXT_EVENT0_TRIG = BIT0,
|
||||
EXT_EVENT1_TRIG = BIT1,
|
||||
GPIO_TRIG = BIT2,
|
||||
TIMER_EXPIRE = BIT3,
|
||||
SDIO_TRIG = BIT4,
|
||||
MAC_TRIG = BIT5,
|
||||
UART0_TRIG = BIT6,
|
||||
UART1_TRIG = BIT7,
|
||||
TOUCH_TRIG = BIT8,
|
||||
SAR_TRIG = BIT9,
|
||||
BT_TRIG = BIT10,
|
||||
RISCV_TRIG = BIT11,
|
||||
XTAL_DEAD_TRIG = BIT12,
|
||||
RISCV_TRAP_TRIG = BIT13,
|
||||
USB_TRIG = BIT14
|
||||
} WAKEUP_REASON;
|
||||
|
||||
typedef enum {
|
||||
DISEN_WAKEUP = NO_SLEEP,
|
||||
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
|
||||
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
|
||||
GPIO_TRIG_EN = GPIO_TRIG,
|
||||
TIMER_EXPIRE_EN = TIMER_EXPIRE,
|
||||
SDIO_TRIG_EN = SDIO_TRIG,
|
||||
MAC_TRIG_EN = MAC_TRIG,
|
||||
UART0_TRIG_EN = UART0_TRIG,
|
||||
UART1_TRIG_EN = UART1_TRIG,
|
||||
TOUCH_TRIG_EN = TOUCH_TRIG,
|
||||
SAR_TRIG_EN = SAR_TRIG,
|
||||
BT_TRIG_EN = BT_TRIG,
|
||||
RISCV_TRIG_EN = RISCV_TRIG,
|
||||
XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
|
||||
RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
|
||||
USB_TRIG_EN = USB_TRIG
|
||||
} WAKEUP_ENABLE;
|
||||
|
||||
/**
|
||||
* @brief Get the reset reason for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return RESET_REASON
|
||||
*/
|
||||
RESET_REASON rtc_get_reset_reason(int cpu_no);
|
||||
|
||||
/**
|
||||
* @brief Get the wakeup cause for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return WAKEUP_REASON
|
||||
*/
|
||||
WAKEUP_REASON rtc_get_wakeup_cause(void);
|
||||
|
||||
typedef void (* esp_rom_wake_func_t)(void);
|
||||
|
||||
/**
|
||||
* @brief Read stored RTC wake function address
|
||||
*
|
||||
* Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
|
||||
* valid means that both stored stub length and stored wake function address are four-byte aligned non-zero values
|
||||
* and the crc check passes
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
|
||||
*/
|
||||
esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
|
||||
|
||||
/**
|
||||
* @brief Store new RTC wake function address
|
||||
*
|
||||
* Set a new RTC wake address function. If a non-NULL function pointer is set then the function
|
||||
* memory is calculated and stored also.
|
||||
*
|
||||
* @param entry_addr Address of function. should be 4-bytes aligned otherwise it will not start from the stub after wake from deepsleep，
|
||||
* if NULL length will be ignored and all registers are cleared to 0.
|
||||
*
|
||||
* @param length length of function in RTC fast memory. should be less than RTC Fast memory size and aligned to 4-bytes.
|
||||
* otherwise all registers are cleared to 0.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
|
||||
|
||||
/**
|
||||
* @brief Suppress ROM log by setting specific RTC control register.
|
||||
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void rtc_suppress_rom_log(void)
|
||||
{
|
||||
/* To disable logging in the ROM, only the least significant bit of the register is used,
|
||||
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
|
||||
* you need to write to this register in the same format.
|
||||
* Namely, the upper 16 bits and lower should be the same.
|
||||
*/
|
||||
REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset(void);
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset_cpu(int cpu_no);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
94
components/esp_rom/esp32s3/include/esp32s3/rom/secure_boot.h
Normal file
94
components/esp_rom/esp32s3/include/esp32s3/rom/secure_boot.h
Normal file
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "ets_sys.h"
|
||||
#include "rsa_pss.h"
|
||||
#include "esp_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
|
||||
typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
|
||||
typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
|
||||
|
||||
/* Anti-FI measure: use full words for success/fail, instead of
|
||||
0/non-zero
|
||||
*/
|
||||
typedef enum {
|
||||
SB_SUCCESS = 0x3A5A5AA5,
|
||||
SB_FAILED = 0x7533885E,
|
||||
} secure_boot_status_t;
|
||||
|
||||
/* Verify bootloader image (reconfigures cache to map), with
|
||||
key digests provided as parameters.)
|
||||
|
||||
Can be used to verify secure boot status before enabling
|
||||
secure boot permanently.
|
||||
|
||||
If result is ETS_OK, the "simple hash" of the bootloader is
|
||||
copied into verified_hash.
|
||||
*/
|
||||
secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
|
||||
|
||||
/* Verify supplied signature against supplied digest, using
|
||||
supplied trusted key digests.
|
||||
|
||||
Doesn't reconfigure cache or any other hardware access.
|
||||
*/
|
||||
secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
|
||||
|
||||
/* Read key digests from efuse. Any revoked/missing digests will be
|
||||
marked as NULL
|
||||
|
||||
Returns 0 if at least one valid digest was found.
|
||||
*/
|
||||
ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
|
||||
|
||||
#define CRC_SIGN_BLOCK_LEN 1196
|
||||
#define SIG_BLOCK_PADDING 4096
|
||||
#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
|
||||
|
||||
/* Secure Boot V2 signature block (up to 3 can be appended) */
|
||||
struct ets_secure_boot_sig_block {
|
||||
uint8_t magic_byte;
|
||||
uint8_t version;
|
||||
uint8_t _reserved1;
|
||||
uint8_t _reserved2;
|
||||
uint8_t image_digest[32];
|
||||
ets_rsa_pubkey_t key;
|
||||
uint8_t signature[384];
|
||||
uint32_t block_crc;
|
||||
uint8_t _padding[16];
|
||||
};
|
||||
|
||||
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "ets_secure_boot_sig_block_t should occupy 1216 Bytes in memory");
|
||||
|
||||
#define SECURE_BOOT_NUM_BLOCKS 3
|
||||
|
||||
/* V2 Secure boot signature sector (up to 3 blocks) */
|
||||
struct ets_secure_boot_signature {
|
||||
ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
|
||||
uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
|
||||
};
|
||||
|
||||
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "ets_secure_boot_signature_t should occupy 4096 Bytes in memory");
|
||||
|
||||
#define MAX_KEY_DIGESTS 3
|
||||
|
||||
struct ets_secure_boot_key_digests {
|
||||
const void *key_digests[MAX_KEY_DIGESTS];
|
||||
bool allow_key_revoke;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
55
components/esp_rom/esp32s3/include/esp32s3/rom/sha.h
Normal file
55
components/esp_rom/esp32s3/include/esp32s3/rom/sha.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "ets_sys.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SHA1 = 0,
|
||||
SHA2_224,
|
||||
SHA2_256,
|
||||
SHA2_384,
|
||||
SHA2_512,
|
||||
SHA2_512224,
|
||||
SHA2_512256,
|
||||
SHA2_512T,
|
||||
SHA_TYPE_MAX
|
||||
} SHA_TYPE;
|
||||
|
||||
typedef struct SHAContext {
|
||||
bool start;
|
||||
bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
|
||||
SHA_TYPE type;
|
||||
uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16
|
||||
unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128
|
||||
uint32_t total_bits[4];
|
||||
} SHA_CTX;
|
||||
|
||||
void ets_sha_enable(void);
|
||||
|
||||
void ets_sha_disable(void);
|
||||
|
||||
ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
|
||||
|
||||
ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
|
||||
|
||||
void ets_sha_get_state(SHA_CTX *ctx);
|
||||
|
||||
void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
|
||||
|
||||
void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
|
||||
|
||||
ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
502
components/esp_rom/esp32s3/include/esp32s3/rom/spi_flash.h
Normal file
502
components/esp_rom/esp32s3/include/esp32s3/rom/spi_flash.h
Normal file
@@ -0,0 +1,502 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*************************************************************
|
||||
* Note
|
||||
*************************************************************
|
||||
* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
|
||||
* used as an SPI master to access Flash and ext-SRAM by
|
||||
* Cache module. It will support Decryto read for Flash,
|
||||
* read/write for ext-SRAM. And SPI1 is also used as an
|
||||
* SPI master for Flash read/write and ext-SRAM read/write.
|
||||
* It will support Encrypto write for Flash.
|
||||
* 2. As an SPI master, SPI support Highest clock to 80M,
|
||||
* however, Flash with 80M Clock should be configured
|
||||
* for different Flash chips. If you want to use 80M
|
||||
* clock We should use the SPI that is certified by
|
||||
* Espressif. However, the certification is not started
|
||||
* at the time, so please use 40M clock at the moment.
|
||||
* 3. SPI Flash can use 2 lines or 4 lines mode. If you
|
||||
* use 2 lines mode, you can save two pad SPIHD and
|
||||
* SPIWP for gpio. ESP32 support configured SPI pad for
|
||||
* Flash, the configuration is stored in efuse and flash.
|
||||
* However, the configurations of pads should be certified
|
||||
* by Espressif. If you use this function, please use 40M
|
||||
* clock at the moment.
|
||||
* 4. ESP32 support to use Common SPI command to configure
|
||||
* Flash to QIO mode, if you failed to configure with fix
|
||||
* command. With Common SPI Command, ESP32 can also provide
|
||||
* a way to use same Common SPI command groups on different
|
||||
* Flash chips.
|
||||
* 5. This functions are not protected by packeting, Please use the
|
||||
*************************************************************
|
||||
*/
|
||||
|
||||
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
|
||||
|
||||
#define SPI0_R_QIO_DUMMY_CYCLELEN 5
|
||||
#define SPI0_R_QIO_ADDR_BITSLEN 23
|
||||
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI0_R_DIO_DUMMY_CYCLELEN 3
|
||||
#define SPI0_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI0_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
|
||||
#define SPI1_R_QIO_ADDR_BITSLEN 23
|
||||
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
|
||||
#define SPI1_R_DIO_ADDR_BITSLEN 23
|
||||
#define SPI1_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI1_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B
|
||||
|
||||
//SPI address register
|
||||
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
|
||||
|
||||
|
||||
typedef void (*spi_flash_func_t)(void);
|
||||
typedef esp_rom_spiflash_result_t (*spi_flash_op_t)(void);
|
||||
typedef esp_rom_spiflash_result_t (*spi_flash_erase_t)(uint32_t);
|
||||
typedef esp_rom_spiflash_result_t (*spi_flash_rd_t)(uint32_t, void*, int);
|
||||
typedef esp_rom_spiflash_result_t (*spi_flash_wr_t)(uint32_t, const uint32_t*, int);
|
||||
typedef esp_rom_spiflash_result_t (*spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
|
||||
typedef esp_rom_spiflash_result_t (*spi_flash_wren_t)(void*);
|
||||
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
|
||||
|
||||
typedef struct {
|
||||
uint8_t pp_addr_bit_len;
|
||||
uint8_t se_addr_bit_len;
|
||||
uint8_t be_addr_bit_len;
|
||||
uint8_t rd_addr_bit_len;
|
||||
uint32_t read_sub_len;
|
||||
uint32_t write_sub_len;
|
||||
spi_flash_op_t unlock;
|
||||
spi_flash_erase_t erase_sector;
|
||||
spi_flash_erase_t erase_block;
|
||||
spi_flash_rd_t read;
|
||||
spi_flash_wr_t write;
|
||||
spi_flash_ewr_t encrypt_write;
|
||||
spi_flash_func_t check_sus;
|
||||
spi_flash_wren_t wren;
|
||||
spi_flash_op_t wait_idle;
|
||||
spi_flash_erase_area_t erase_area;
|
||||
} spiflash_legacy_funcs_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t data_length;
|
||||
uint8_t read_cmd0;
|
||||
uint8_t read_cmd1;
|
||||
uint8_t write_cmd;
|
||||
uint16_t data_mask;
|
||||
uint16_t data;
|
||||
} esp_rom_spiflash_common_cmd_t;
|
||||
|
||||
/**
|
||||
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @param uint8_t legacy: always keeping false.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
|
||||
|
||||
/**
|
||||
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t *status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
|
||||
|
||||
/**
|
||||
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t *status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
|
||||
|
||||
/**
|
||||
* @brief Write status to Flash status register.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t status_value : Value to .
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
|
||||
|
||||
/**
|
||||
* @brief Use a command to Read Flash status register.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t*status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
|
||||
|
||||
/**
|
||||
* @brief Config SPI Flash read mode when init.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
|
||||
*
|
||||
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Config SPI Flash clock divisor.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t freqdiv: clock divisor.
|
||||
*
|
||||
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
|
||||
|
||||
/**
|
||||
* @brief Clear all SR bits except QE bit.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
|
||||
|
||||
/**
|
||||
* @brief Clear all SR bits except QE bit.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
|
||||
|
||||
/**
|
||||
* @brief Update SPI Flash parameter.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
|
||||
*
|
||||
* @param uint32_t chip_size : The Flash size.
|
||||
*
|
||||
* @param uint32_t block_size : The Flash block size.
|
||||
*
|
||||
* @param uint32_t sector_size : The Flash sector size.
|
||||
*
|
||||
* @param uint32_t page_size : The Flash page size.
|
||||
*
|
||||
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
|
||||
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
|
||||
|
||||
/**
|
||||
* @brief Erase whole flash chip.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
|
||||
|
||||
/**
|
||||
* @brief Erase a 64KB block of flash
|
||||
* Uses SPI flash command D8H.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t block_num : Which block to erase.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
|
||||
|
||||
/**
|
||||
* @brief Erase a sector of flash.
|
||||
* Uses SPI flash command 20H.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t sector_num : Which sector to erase.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
|
||||
|
||||
/**
|
||||
* @brief Erase some sectors.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
|
||||
*
|
||||
* @param uint32_t area_len : Length to erase, should be sector aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
|
||||
|
||||
/**
|
||||
* @brief Write Data to Flash, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
|
||||
*
|
||||
* @param const uint32_t *src : The pointer to data which is to write.
|
||||
*
|
||||
* @param uint32_t len : Length to write, should be 4 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
|
||||
|
||||
/**
|
||||
* @brief Read Data from Flash, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
|
||||
*
|
||||
* @param uint32_t *dest : The buf to read the data.
|
||||
*
|
||||
* @param uint32_t len : Length to read, should be 4 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
|
||||
|
||||
/**
|
||||
* @brief SPI1 go into encrypto mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_write_encrypted_enable(void);
|
||||
|
||||
/**
|
||||
* @brief SPI1 go out of encrypto mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_write_encrypted_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Write data to flash with transparent encryption.
|
||||
* @note Sectors to be written should already be erased.
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
|
||||
*
|
||||
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
|
||||
* be 32 bit aligned and the content of the data will be
|
||||
* modified by the encryption function.
|
||||
*
|
||||
* @param uint32_t len : Length to write, should be 32 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
|
||||
|
||||
|
||||
/** @brief Wait until SPI flash write operation is complete
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* Reads the Write In Progress bit of the SPI flash status register,
|
||||
* repeats until this bit is zero (indicating write complete).
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
|
||||
|
||||
|
||||
/** @brief Enable Quad I/O pin functions
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* Sets the HD & WP pin functions for Quad I/O modes, based on the
|
||||
* efuse SPI pin configuration.
|
||||
*
|
||||
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
|
||||
*
|
||||
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
|
||||
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
|
||||
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
|
||||
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
|
||||
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
|
||||
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
|
||||
*/
|
||||
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
|
||||
|
||||
/**
|
||||
* @brief Clear WEL bit unconditionally.
|
||||
*
|
||||
* @return always ESP_ROM_SPIFLASH_RESULT_OK
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Set WREN bit.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @return always ESP_ROM_SPIFLASH_RESULT_OK
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
|
||||
*
|
||||
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
|
||||
|
||||
/**
|
||||
* @brief Set SPI Flash pad drivers.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t wp_gpio_num: WP gpio number.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
|
||||
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
|
||||
* Values usually read from flash by rom code, function usually called by rom code.
|
||||
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
|
||||
|
||||
/**
|
||||
* @brief Select SPI Flash function for pads.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
|
||||
|
||||
/**
|
||||
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
|
||||
*
|
||||
* @return uint16_t 0 : do not send command any more.
|
||||
* 1 : go to the next command.
|
||||
* n > 1 : skip (n - 1) commands.
|
||||
*/
|
||||
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
|
||||
|
||||
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
97
components/esp_rom/esp32s3/include/esp32s3/rom/tjpgd.h
Normal file
97
components/esp_rom/esp32s3/include/esp32s3/rom/tjpgd.h
Normal file
@@ -0,0 +1,97 @@
|
||||
/*----------------------------------------------------------------------------/
|
||||
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------*/
|
||||
#ifndef _TJPGDEC
|
||||
#define _TJPGDEC
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* System Configurations */
|
||||
|
||||
#define JD_SZBUF 512 /* Size of stream input buffer */
|
||||
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
|
||||
#define JD_USE_SCALE 1 /* Use descaling feature for output */
|
||||
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* These types must be 16-bit, 32-bit or larger integer */
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* These types must be 8-bit integer */
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
/* These types must be 16-bit integer */
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
|
||||
/* These types must be 32-bit integer */
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
|
||||
/* Error code */
|
||||
typedef enum {
|
||||
JDR_OK = 0, /* 0: Succeeded */
|
||||
JDR_INTR, /* 1: Interrupted by output function */
|
||||
JDR_INP, /* 2: Device error or wrong termination of input stream */
|
||||
JDR_MEM1, /* 3: Insufficient memory pool for the image */
|
||||
JDR_MEM2, /* 4: Insufficient stream input buffer */
|
||||
JDR_PAR, /* 5: Parameter error */
|
||||
JDR_FMT1, /* 6: Data format error (may be damaged data) */
|
||||
JDR_FMT2, /* 7: Right format but not supported */
|
||||
JDR_FMT3 /* 8: Not supported JPEG standard */
|
||||
} JRESULT;
|
||||
|
||||
|
||||
|
||||
/* Rectangular structure */
|
||||
typedef struct {
|
||||
WORD left, right, top, bottom;
|
||||
} JRECT;
|
||||
|
||||
|
||||
|
||||
/* Decompressor object structure */
|
||||
typedef struct JDEC JDEC;
|
||||
struct JDEC {
|
||||
UINT dctr; /* Number of bytes available in the input buffer */
|
||||
BYTE *dptr; /* Current data read ptr */
|
||||
BYTE *inbuf; /* Bit stream input buffer */
|
||||
BYTE dmsk; /* Current bit in the current read byte */
|
||||
BYTE scale; /* Output scaling ratio */
|
||||
BYTE msx, msy; /* MCU size in unit of block (width, height) */
|
||||
BYTE qtid[3]; /* Quantization table ID of each component */
|
||||
SHORT dcv[3]; /* Previous DC element of each component */
|
||||
WORD nrst; /* Restart interval */
|
||||
UINT width, height; /* Size of the input image (pixel) */
|
||||
BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
|
||||
WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */
|
||||
BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
|
||||
LONG *qttbl[4]; /* Dequaitizer tables [id] */
|
||||
void *workbuf; /* Working buffer for IDCT and RGB output */
|
||||
BYTE *mcubuf; /* Working buffer for the MCU */
|
||||
void *pool; /* Pointer to available memory pool */
|
||||
UINT sz_pool; /* Size of memory pool (bytes available) */
|
||||
UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */
|
||||
void *device; /* Pointer to I/O device identifier for the session */
|
||||
};
|
||||
|
||||
/* TJpgDec API functions */
|
||||
JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *);
|
||||
JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TJPGDEC */
|
||||
337
components/esp_rom/esp32s3/include/esp32s3/rom/uart.h
Normal file
337
components/esp_rom/esp32s3/include/esp32s3/rom/uart.h
Normal file
@@ -0,0 +1,337 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ets_sys.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/uart_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup uart_apis, uart configuration and communication related apis
|
||||
* @brief uart apis
|
||||
*/
|
||||
|
||||
/** @addtogroup uart_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RX_BUFF_SIZE 0x400
|
||||
#define TX_BUFF_SIZE 100
|
||||
|
||||
//uart int enable register ctrl bits
|
||||
#define UART_RCV_INTEN BIT0
|
||||
#define UART_TRX_INTEN BIT1
|
||||
#define UART_LINE_STATUS_INTEN BIT2
|
||||
|
||||
//uart int identification ctrl bits
|
||||
#define UART_INT_FLAG_MASK 0x0E
|
||||
|
||||
//uart fifo ctrl bits
|
||||
#define UART_CLR_RCV_FIFO BIT1
|
||||
#define UART_CLR_TRX_FIFO BIT2
|
||||
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
|
||||
|
||||
//uart line control bits
|
||||
#define UART_DIV_LATCH_ACCESS_BIT BIT7
|
||||
|
||||
//uart line status bits
|
||||
#define UART_RCV_DATA_RDY_FLAG BIT0
|
||||
#define UART_RCV_OVER_FLOW_FLAG BIT1
|
||||
#define UART_RCV_PARITY_ERR_FLAG BIT2
|
||||
#define UART_RCV_FRAME_ERR_FLAG BIT3
|
||||
#define UART_BRK_INT_FLAG BIT4
|
||||
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
|
||||
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
|
||||
#define UART_RCV_ERR_FLAG BIT7
|
||||
|
||||
//send and receive message frame head
|
||||
#define FRAME_FLAG 0x7E
|
||||
|
||||
typedef enum {
|
||||
UART_LINE_STATUS_INT_FLAG = 0x06,
|
||||
UART_RCV_FIFO_INT_FLAG = 0x04,
|
||||
UART_RCV_TMOUT_INT_FLAG = 0x0C,
|
||||
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
|
||||
} UartIntType; //consider bit0 for int_flag
|
||||
|
||||
typedef enum {
|
||||
RCV_ONE_BYTE = 0x0,
|
||||
RCV_FOUR_BYTE = 0x1,
|
||||
RCV_EIGHT_BYTE = 0x2,
|
||||
RCV_FOURTEEN_BYTE = 0x3
|
||||
} UartRcvFifoTrgLvl;
|
||||
|
||||
typedef enum {
|
||||
FIVE_BITS = 0x0,
|
||||
SIX_BITS = 0x1,
|
||||
SEVEN_BITS = 0x2,
|
||||
EIGHT_BITS = 0x3
|
||||
} UartBitsNum4Char;
|
||||
|
||||
typedef enum {
|
||||
ONE_STOP_BIT = 1,
|
||||
ONE_HALF_STOP_BIT = 2,
|
||||
TWO_STOP_BIT = 3
|
||||
} UartStopBitsNum;
|
||||
|
||||
typedef enum {
|
||||
NONE_BITS = 0,
|
||||
ODD_BITS = 2,
|
||||
EVEN_BITS = 3
|
||||
|
||||
} UartParityMode;
|
||||
|
||||
typedef enum {
|
||||
STICK_PARITY_DIS = 0,
|
||||
STICK_PARITY_EN = 2
|
||||
} UartExistParity;
|
||||
|
||||
typedef enum {
|
||||
BIT_RATE_9600 = 9600,
|
||||
BIT_RATE_19200 = 19200,
|
||||
BIT_RATE_38400 = 38400,
|
||||
BIT_RATE_57600 = 57600,
|
||||
BIT_RATE_115200 = 115200,
|
||||
BIT_RATE_230400 = 230400,
|
||||
BIT_RATE_460800 = 460800,
|
||||
BIT_RATE_921600 = 921600
|
||||
} UartBautRate;
|
||||
|
||||
typedef enum {
|
||||
NONE_CTRL,
|
||||
HARDWARE_CTRL,
|
||||
XON_XOFF_CTRL
|
||||
} UartFlowCtrl;
|
||||
|
||||
typedef enum {
|
||||
EMPTY,
|
||||
UNDER_WRITE,
|
||||
WRITE_OVER
|
||||
} RcvMsgBuffState;
|
||||
|
||||
typedef struct {
|
||||
uint8_t *pRcvMsgBuff;
|
||||
uint8_t *pWritePos;
|
||||
uint8_t *pReadPos;
|
||||
uint8_t TrigLvl;
|
||||
RcvMsgBuffState BuffState;
|
||||
} RcvMsgBuff;
|
||||
|
||||
typedef struct {
|
||||
uint32_t TrxBuffSize;
|
||||
uint8_t *pTrxBuff;
|
||||
} TrxMsgBuff;
|
||||
|
||||
typedef enum {
|
||||
BAUD_RATE_DET,
|
||||
WAIT_SYNC_FRM,
|
||||
SRCH_MSG_HEAD,
|
||||
RCV_MSG_BODY,
|
||||
RCV_ESC_CHAR,
|
||||
} RcvMsgState;
|
||||
|
||||
typedef struct {
|
||||
UartBautRate baut_rate;
|
||||
UartBitsNum4Char data_bits;
|
||||
UartExistParity exist_parity;
|
||||
UartParityMode parity; // chip size in byte
|
||||
UartStopBitsNum stop_bits;
|
||||
UartFlowCtrl flow_ctrl;
|
||||
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
|
||||
RcvMsgBuff rcv_buff;
|
||||
// TrxMsgBuff trx_buff;
|
||||
RcvMsgState rcv_state;
|
||||
int received;
|
||||
} UartDevice;
|
||||
|
||||
/**
|
||||
* @brief Init uart device struct value and reset uart0/uart1 rx.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uartAttach(void *rxBuffer);
|
||||
|
||||
/**
|
||||
* @brief Init uart0 or uart1 for UART download booting mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, else for UART1.
|
||||
*
|
||||
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Uart_Init(uint8_t uart_no, uint32_t clock);
|
||||
|
||||
/**
|
||||
* @brief Modify uart baudrate.
|
||||
* This function will reset RX/TX fifo for uart.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
|
||||
|
||||
/**
|
||||
* @brief Switch printf channel of uart_tx_one_char.
|
||||
* Please do not call this function when printf.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_tx_switch(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Output a char to printf channel, wait until fifo not full.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS uart_tx_one_char(uint8_t TxChar);
|
||||
|
||||
/**
|
||||
* @brief Output a char to message exchange channel, wait until fifo not full.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS uart_tx_one_char2(uint8_t TxChar);
|
||||
|
||||
/**
|
||||
* @brief Wait until uart tx full empty.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void uart_tx_flush(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Wait until uart tx full empty and the last char send ok.
|
||||
*
|
||||
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2
|
||||
*
|
||||
* The function defined in ROM code has a bug, so we define the correct version
|
||||
* here for compatibility.
|
||||
*/
|
||||
void uart_tx_wait_idle(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Get an input char from message channel.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pRxChar : the pointer to store the char.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS uart_rx_one_char(uint8_t *pRxChar);
|
||||
|
||||
/**
|
||||
* @brief Get an input char from message channel, wait until successful.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return char : input char value.
|
||||
*/
|
||||
char uart_rx_one_char_block(void);
|
||||
|
||||
/**
|
||||
* @brief Get an input string line from message channel.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pString : the pointer to store the string.
|
||||
*
|
||||
* @param uint8_t MaxStrlen : the max string length, include '\0'.
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
|
||||
|
||||
/**
|
||||
* @brief Get an char from receive buffer.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
|
||||
*
|
||||
* @param uint8_t *pRxByte : the pointer to store the char.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
|
||||
|
||||
/**
|
||||
* @brief Get uart configuration struct.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UartDevice * : uart configuration struct pointer.
|
||||
*/
|
||||
UartDevice *GetUartDevice(void);
|
||||
|
||||
/**
|
||||
* @brief Send an packet to download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *p : the pointer to output string.
|
||||
*
|
||||
* @param int len : the string length.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void send_packet(uint8_t *p, int len);
|
||||
|
||||
/**
|
||||
* @brief Receive an packet from download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *p : the pointer to input string.
|
||||
*
|
||||
* @param int len : If string length > len, the string will be truncated.
|
||||
*
|
||||
* @param uint8_t is_sync : 0, only one UART module;
|
||||
* 1, two UART modules.
|
||||
*
|
||||
* @return int : the length of the string.
|
||||
*/
|
||||
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
|
||||
|
||||
/**
|
||||
* @brief Initialize the USB ACM UART
|
||||
* Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have.
|
||||
*
|
||||
* @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code
|
||||
* @param cdc_acm_work_mem_len Length of work mem
|
||||
*/
|
||||
void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
|
||||
|
||||
extern UartDevice UartDev;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
226
components/esp_rom/esp32s3/include/esp32s3/rom/usb/cdc_acm.h
Normal file
226
components/esp_rom/esp32s3/include/esp32s3/rom/usb/cdc_acm.h
Normal file
@@ -0,0 +1,226 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015, 2016 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef void cdc_acm_device;
|
||||
extern cdc_acm_device *uart_acm_dev;
|
||||
|
||||
#define ACM_BYTES_PER_TX 64
|
||||
|
||||
//ACM statuses are negative to distinguish from USB_DC_* status codes
|
||||
#define ACM_STATUS_LINESTATE_CHANGED -1
|
||||
#define ACM_STATUS_LINECODING_CHANGED -2
|
||||
#define ACM_STATUS_TX -3
|
||||
#define ACM_STATUS_RX -4
|
||||
|
||||
typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status);
|
||||
|
||||
/**
|
||||
* @brief Get amount of received characters in buffer
|
||||
*
|
||||
* @returns character count
|
||||
*/
|
||||
|
||||
int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev);
|
||||
|
||||
|
||||
/*
|
||||
* @brief Output a character in polled mode.
|
||||
*
|
||||
* The UART poll method for USB UART is simulated by waiting till
|
||||
* we get the next BULK In upcall from the USB device controller or 100 ms.
|
||||
*
|
||||
* @return the same character which is sent
|
||||
*/
|
||||
unsigned char cdc_acm_poll_out(cdc_acm_device *dev, unsigned char c);
|
||||
|
||||
/**
|
||||
* @brief Fill FIFO with data
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
* @param tx_data Data to transmit.
|
||||
* @param len Number of bytes to send.
|
||||
*
|
||||
* @return Number of bytes sent.
|
||||
*/
|
||||
int cdc_acm_fifo_fill(cdc_acm_device *dev, const uint8_t *tx_data, int len);
|
||||
|
||||
/**
|
||||
* @brief Read data from FIFO
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
* @param rx_data Pointer to data container.
|
||||
* @param size Container size.
|
||||
*
|
||||
* @return Number of bytes read.
|
||||
*/
|
||||
int cdc_acm_fifo_read(cdc_acm_device *dev, uint8_t *rx_data, const int size);
|
||||
|
||||
/**
|
||||
* @brief Enable TX interrupt
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return N/A.
|
||||
*/
|
||||
void cdc_acm_irq_tx_enable(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Disable TX interrupt
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return N/A.
|
||||
*/
|
||||
void cdc_acm_irq_tx_disable(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Check if Tx IRQ has been raised
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return 1 if a Tx IRQ is pending, 0 otherwise.
|
||||
*/
|
||||
int cdc_acm_irq_tx_ready(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Enable RX interrupt
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return N/A
|
||||
*/
|
||||
void cdc_acm_irq_rx_enable(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Disable RX interrupt
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return N/A.
|
||||
*/
|
||||
void cdc_acm_irq_rx_disable(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Enable line state interrupt
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return N/A.
|
||||
*/
|
||||
void cdc_acm_irq_state_enable(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Disable line state interrupt
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return N/A.
|
||||
*/
|
||||
void cdc_acm_irq_state_disable(cdc_acm_device *dev);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if Rx IRQ has been raised
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return 1 if an IRQ is ready, 0 otherwise.
|
||||
*/
|
||||
int cdc_acm_irq_rx_ready(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Check if Tx or Rx IRQ is pending
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
*
|
||||
* @return 1 if a Tx or Rx IRQ is pending, 0 otherwise.
|
||||
*/
|
||||
int cdc_acm_irq_is_pending(cdc_acm_device *dev);
|
||||
|
||||
/**
|
||||
* @brief Set the callback function pointer for IRQ.
|
||||
*
|
||||
* @param dev CDC ACM device struct.
|
||||
* @param cb Callback function pointer.
|
||||
*
|
||||
* @return N/A
|
||||
*/
|
||||
void cdc_acm_irq_callback_set(cdc_acm_device *dev, uart_irq_callback_t cb);
|
||||
|
||||
/**
|
||||
* @brief Manipulate line control for UART.
|
||||
*
|
||||
* @param dev CDC ACM device struct
|
||||
* @param ctrl The line control to be manipulated
|
||||
* @param val Value to set the line control
|
||||
*
|
||||
* @return 0 if successful, failed otherwise.
|
||||
*/
|
||||
int cdc_acm_line_ctrl_set(cdc_acm_device *dev, uint32_t ctrl, uint32_t val);
|
||||
|
||||
/**
|
||||
* @brief Manipulate line control for UART.
|
||||
*
|
||||
* @param dev CDC ACM device struct
|
||||
* @param ctrl The line control to be manipulated
|
||||
* @param val Value to set the line control
|
||||
*
|
||||
* @return 0 if successful, failed otherwise.
|
||||
*/
|
||||
int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize UART channel
|
||||
*
|
||||
* This routine is called to reset the chip in a quiescent state.
|
||||
* It is assumed that this function is called only once per UART.
|
||||
*
|
||||
* @param mem_chunk Memory chunk to use for internal use
|
||||
* @param mem_chunk_size Size of the memory chunk in bytes
|
||||
*
|
||||
* @return dev or NULL
|
||||
*/
|
||||
cdc_acm_device *cdc_acm_init(void *mem_chunk, int mem_chunk_size);
|
||||
|
||||
|
||||
/** Common line controls for UART.*/
|
||||
#define LINE_CTRL_BAUD_RATE (1 << 0)
|
||||
#define LINE_CTRL_RTS (1 << 1)
|
||||
#define LINE_CTRL_DTR (1 << 2)
|
||||
#define LINE_CTRL_DCD (1 << 3)
|
||||
#define LINE_CTRL_DSR (1 << 4)
|
||||
|
||||
/* Common communication errors for UART.*/
|
||||
|
||||
/** @brief Overrun error */
|
||||
#define UART_ERROR_OVERRUN (1 << 0)
|
||||
|
||||
/** @brief Parity error */
|
||||
#define UART_ERROR_PARITY (1 << 1)
|
||||
|
||||
/** @brief Framing error */
|
||||
#define UART_ERROR_FRAMING (1 << 2)
|
||||
|
||||
/**
|
||||
* @brief Break interrupt error:
|
||||
*
|
||||
* A break interrupt was received. This happens when the serial input is
|
||||
* held at a logic '0' state for longer than the sum of start time + data bits
|
||||
* + parity + stop bits.
|
||||
*/
|
||||
#define UART_ERROR_BREAK (1 << 3)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int chip_usb_dw_init(void);
|
||||
int chip_usb_dw_did_persist(void);
|
||||
void chip_usb_dw_prepare_persist(void);
|
||||
uint32_t chip_usb_get_persist_flags(void);
|
||||
void chip_usb_set_persist_flags(uint32_t flags);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
172
components/esp_rom/esp32s3/include/esp32s3/rom/usb/cpio.h
Normal file
172
components/esp_rom/esp32s3/include/esp32s3/rom/usb/cpio.h
Normal file
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* Archive to parse cpio data in the newc and crc formats. Generate a cpio archive like that by e.g.
|
||||
* find . | cpio -o -H newc > archive.cpio
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CPIO_MODE_FILETYPE_MASK 0xF000
|
||||
#define CPIO_MODE_FILETYPE_SOCKET 0xC000
|
||||
#define CPIO_MODE_FILETYPE_SYMLINK 0xA000
|
||||
#define CPIO_MODE_FILETYPE_REGULAR 0x8000
|
||||
#define CPIO_MODE_FILETYPE_BLOCKDEV 0x6000
|
||||
#define CPIO_MODE_FILETYPE_DIR 0x4000
|
||||
#define CPIO_MODE_FILETYPE_CHARDEV 0x2000
|
||||
#define CPIO_MODE_FILETYPE_FIFO 0x1000
|
||||
#define CPIO_MODE_SUID 0x0800
|
||||
#define CPIO_MODE_SGID 0x0400
|
||||
#define CPIO_MODE_STICKY 0x0200
|
||||
|
||||
typedef struct {
|
||||
size_t filesize;
|
||||
char *name;
|
||||
uint32_t mode;
|
||||
uint32_t check;
|
||||
} cpio_file_t;
|
||||
|
||||
typedef enum {
|
||||
CPIO_RET_MORE = 0,
|
||||
CPIO_RET_DONE,
|
||||
CPIO_RET_ERR
|
||||
} cpio_ret_t;
|
||||
|
||||
typedef struct cpio_handle_data_t cpio_handle_data_t;
|
||||
typedef cpio_handle_data_t *cpio_handle_t;
|
||||
|
||||
typedef enum {
|
||||
CPIO_RSN_FILE_ALL = 0,
|
||||
CPIO_RSN_FILE_INITIAL,
|
||||
CPIO_RSN_FILE_MORE,
|
||||
CPIO_RSN_FILE_END
|
||||
} cpio_callback_reason_t;
|
||||
|
||||
|
||||
/**
|
||||
* Callback for cpio file data.
|
||||
*
|
||||
* This callback will be called by the library to indicate data for a file is available.
|
||||
*
|
||||
* For files in the cpio archive that fit entirely in the internal buffer, or when no internal
|
||||
* buffer is available, are entirely contained in the buffer fed to cpio_feed(), this callback
|
||||
* is only called once, with reason=CPIO_RNS_FILE_ALL. fileinfo will contain the information
|
||||
* for that specific file (name, size, ...), buff_offset will be 0, buff_len is the file
|
||||
* size and buff contains all the information for the file.
|
||||
*
|
||||
* For files that do not fit in the buffer, this callback will be called multiple times.
|
||||
* The initial time with reason=CPIO_RSN_FILE_INITIAL, when more data is available with
|
||||
* CPIO_RSN_FILE_MORE and finally with CPIO_RSN_FILE_END. For these calls, fileinfo
|
||||
* will again contain file information. buff will be the information contained in the
|
||||
* file at offset buff_offset, and the length of this buffer will be in buff_len.
|
||||
*
|
||||
* The library guarantees to feed all file data to the callback consequitively, so
|
||||
* within the same file, the buff_offset from a call will always be (buff_offset+buff_len)
|
||||
* from the call before that. If cpio_start is
|
||||
*
|
||||
* The library also guarantees every file in the cpio archive will either generate a single
|
||||
* callback call with CPIO_RSN_ALL, or multiple with in sequence CPIO_RSN_FILE_INITIAL, 0 or
|
||||
* more CPIO_RSN_FILE_MORE and finally a CPIO_RSN_FILE_END.
|
||||
*
|
||||
* When a non-zero buffer size is passed to cpio_start, the library guarantees that all callback
|
||||
* calls with a reason of CPIO_RSN_FILE_INITIAL and CPIO_RSN_FILE_MORE will have a buffer
|
||||
* filled with exactly this amount of bytes.
|
||||
*
|
||||
*/
|
||||
typedef void (*cpio_callback_t)(cpio_callback_reason_t reason, cpio_file_t *fileinfo, size_t buff_offset, size_t buff_len, char *buff, void *arg);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize a cpio handle.
|
||||
*
|
||||
* Call this to start parsing a cpio archive. You can set the callback that handles the
|
||||
* files/data here.
|
||||
*
|
||||
* @param callback The callback that will handle the data of the files inside the cpio archive
|
||||
*
|
||||
* @param cbarg User-supplied argument. The callback will be called with this as an argument.
|
||||
*
|
||||
* @param buflen Length of internal buffer used.
|
||||
* If this is zero, the callback will be called with data that lives in the data buffer
|
||||
* supplied to the cpio library by whomever called cpio_feed(). Because this library has
|
||||
* no power over that buffer, the callback can be passed as little as 1 and as many as
|
||||
* INT_MAX bytes at a time.
|
||||
* If this is non-zero, the library will allocate an internal buffer of this size. All
|
||||
* cpio_feed()-calls will be rebuffered, and the callback is guaranteed to only be called
|
||||
* with this many bytes in the buffer, given there's enough data in the file to fill it.
|
||||
*
|
||||
* @param memchunk Chunk of memory to allocate everything (handle, I/O buffer, filename buffer) in. Minimum size
|
||||
* (estimate) is 160+buflen+sizeof(largest filename/path).
|
||||
* @param memchunklen Size of the mem chunk
|
||||
*
|
||||
* @return
|
||||
* - Success: A pointer to a cpio handle
|
||||
* - Error: NULL
|
||||
*
|
||||
*/
|
||||
cpio_handle_t cpio_start(cpio_callback_t callback, void *cbarg, size_t buflen, void *memchunk, int memchunklen);
|
||||
|
||||
/**
|
||||
* @brief Feed data from a cpio archive into the library
|
||||
*
|
||||
* This routine is used to feed consecutive data of the cpio archive into the library. While processing,
|
||||
* the library can call the callback function one or more times if needed.
|
||||
*
|
||||
* @param cpio Handle obtained by calling cpio_start()
|
||||
*
|
||||
* @param buffer Pointer to buffer containing cpio archive data
|
||||
*
|
||||
* @param len Length of the buffer, in bytes
|
||||
*
|
||||
* @return
|
||||
* - CPIO_RET_MORE: CPIO archive isn't done yet, please feed more data.
|
||||
* - CPIO_RET_DONE: CPUI archive is finished.
|
||||
* - CPIO_RET_ERR: Invalid CPIO archive data; decoding aborted.
|
||||
*
|
||||
*/
|
||||
cpio_ret_t cpio_feed(cpio_handle_t cpio, char *buffer, int len);
|
||||
|
||||
/**
|
||||
* @brief Indicate there is no more cpio data to be fed into the archive
|
||||
*
|
||||
* This call is to be called when the source data is exhausted. Normally, the library can find the end of the
|
||||
* cpio archive by looking for the end marker,
|
||||
*
|
||||
* @param timer_conf Pointer of LEDC timer configure struct
|
||||
*
|
||||
*
|
||||
* @return
|
||||
* - CPIO_RET_DONE on success
|
||||
* - CPIO_RET_ERR when cpio archive is invalid
|
||||
*
|
||||
*/
|
||||
cpio_ret_t cpio_done(cpio_handle_t cpio);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Free the memory allocated for a cpio handle.
|
||||
*
|
||||
* @param cpio Handle obtained by calling cpio_start()
|
||||
*
|
||||
* @return
|
||||
* - CPIO_RET_DONE on success
|
||||
*
|
||||
*/
|
||||
cpio_ret_t cpio_destroy(cpio_handle_t cpio);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
171
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_cdc.h
Normal file
171
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_cdc.h
Normal file
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief USB Communications Device Class (CDC) public header
|
||||
*
|
||||
* Header follows the Class Definitions for
|
||||
* Communications Devices Specification (CDC120-20101103-track.pdf),
|
||||
* PSTN Devices Specification (PSTN120.pdf) and
|
||||
* Ethernet Control Model Devices Specification (ECM120.pdf).
|
||||
* Header is limited to ACM and ECM Subclasses.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** CDC Specification release number in BCD format */
|
||||
#define CDC_SRN_1_20 0x0120
|
||||
|
||||
/** Communications Class Subclass Codes */
|
||||
#define ACM_SUBCLASS 0x02
|
||||
#define ECM_SUBCLASS 0x06
|
||||
#define EEM_SUBCLASS 0x0c
|
||||
|
||||
/** Communications Class Protocol Codes */
|
||||
#define AT_CMD_V250_PROTOCOL 0x01
|
||||
#define EEM_PROTOCOL 0x07
|
||||
|
||||
/**
|
||||
* @brief Data Class Interface Codes
|
||||
* @note CDC120-20101103-track.pdf, 4.5, Table 6
|
||||
*/
|
||||
#define DATA_INTERFACE_CLASS 0x0A
|
||||
|
||||
/**
|
||||
* @brief Values for the bDescriptorType Field
|
||||
* @note CDC120-20101103-track.pdf, 5.2.3, Table 12
|
||||
*/
|
||||
#define CS_INTERFACE 0x24
|
||||
#define CS_ENDPOINT 0x25
|
||||
|
||||
/**
|
||||
* @brief bDescriptor SubType for Communications
|
||||
* Class Functional Descriptors
|
||||
* @note CDC120-20101103-track.pdf, 5.2.3, Table 13
|
||||
*/
|
||||
#define HEADER_FUNC_DESC 0x00
|
||||
#define CALL_MANAGEMENT_FUNC_DESC 0x01
|
||||
#define ACM_FUNC_DESC 0x02
|
||||
#define UNION_FUNC_DESC 0x06
|
||||
#define ETHERNET_FUNC_DESC 0x0F
|
||||
|
||||
/**
|
||||
* @brief PSTN Subclass Specific Requests
|
||||
* for ACM devices
|
||||
* @note PSTN120.pdf, 6.3, Table 13
|
||||
*/
|
||||
#define CDC_SEND_ENC_CMD 0x00
|
||||
#define CDC_GET_ENC_RSP 0x01
|
||||
#define SET_LINE_CODING 0x20
|
||||
#define GET_LINE_CODING 0x21
|
||||
#define SET_CONTROL_LINE_STATE 0x22
|
||||
|
||||
/** Control Signal Bitmap Values for SetControlLineState */
|
||||
#define SET_CONTROL_LINE_STATE_RTS 0x02
|
||||
#define SET_CONTROL_LINE_STATE_DTR 0x01
|
||||
|
||||
/** UART State Bitmap Values */
|
||||
#define SERIAL_STATE_OVERRUN 0x40
|
||||
#define SERIAL_STATE_PARITY 0x20
|
||||
#define SERIAL_STATE_FRAMING 0x10
|
||||
#define SERIAL_STATE_RING 0x08
|
||||
#define SERIAL_STATE_BREAK 0x04
|
||||
#define SERIAL_STATE_TX_CARRIER 0x02
|
||||
#define SERIAL_STATE_RX_CARRIER 0x01
|
||||
|
||||
/**
|
||||
* @brief Class-Specific Request Codes for Ethernet subclass
|
||||
* @note ECM120.pdf, 6.2, Table 6
|
||||
*/
|
||||
#define SET_ETHERNET_MULTICAST_FILTERS 0x40
|
||||
#define SET_ETHERNET_PM_FILTER 0x41
|
||||
#define GET_ETHERNET_PM_FILTER 0x42
|
||||
#define SET_ETHERNET_PACKET_FILTER 0x43
|
||||
#define GET_ETHERNET_STATISTIC 0x44
|
||||
|
||||
/** Ethernet Packet Filter Bitmap */
|
||||
#define PACKET_TYPE_MULTICAST 0x10
|
||||
#define PACKET_TYPE_BROADCAST 0x08
|
||||
#define PACKET_TYPE_DIRECTED 0x04
|
||||
#define PACKET_TYPE_ALL_MULTICAST 0x02
|
||||
#define PACKET_TYPE_PROMISCUOUS 0x01
|
||||
|
||||
/** Header Functional Descriptor */
|
||||
struct cdc_header_descriptor {
|
||||
uint8_t bFunctionLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bDescriptorSubtype;
|
||||
uint16_t bcdCDC;
|
||||
} __packed;
|
||||
|
||||
/** Union Interface Functional Descriptor */
|
||||
struct cdc_union_descriptor {
|
||||
uint8_t bFunctionLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bDescriptorSubtype;
|
||||
uint8_t bControlInterface;
|
||||
uint8_t bSubordinateInterface0;
|
||||
} __packed;
|
||||
|
||||
/** Call Management Functional Descriptor */
|
||||
struct cdc_cm_descriptor {
|
||||
uint8_t bFunctionLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bDescriptorSubtype;
|
||||
uint8_t bmCapabilities;
|
||||
uint8_t bDataInterface;
|
||||
} __packed;
|
||||
|
||||
/** Abstract Control Management Functional Descriptor */
|
||||
struct cdc_acm_descriptor {
|
||||
uint8_t bFunctionLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bDescriptorSubtype;
|
||||
uint8_t bmCapabilities;
|
||||
} __packed;
|
||||
|
||||
|
||||
/** Data structure for GET_LINE_CODING / SET_LINE_CODING class requests */
|
||||
struct cdc_acm_line_coding {
|
||||
uint32_t dwDTERate;
|
||||
uint8_t bCharFormat;
|
||||
uint8_t bParityType;
|
||||
uint8_t bDataBits;
|
||||
} __packed;
|
||||
|
||||
/** Data structure for the notification about SerialState */
|
||||
struct cdc_acm_notification {
|
||||
uint8_t bmRequestType;
|
||||
uint8_t bNotificationType;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
uint16_t data;
|
||||
} __packed;
|
||||
|
||||
/** Ethernet Networking Functional Descriptor */
|
||||
struct cdc_ecm_descriptor {
|
||||
uint8_t bFunctionLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bDescriptorSubtype;
|
||||
uint8_t iMACAddress;
|
||||
uint32_t bmEthernetStatistics;
|
||||
uint16_t wMaxSegmentSize;
|
||||
uint16_t wNumberMCFilters;
|
||||
uint8_t bNumberPowerFilters;
|
||||
} __packed;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
196
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_common.h
Normal file
196
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_common.h
Normal file
@@ -0,0 +1,196 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015,2016 Intel Corporation
|
||||
* SPDX-FileContributor: 2017 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief useful constants and macros for the USB application
|
||||
*
|
||||
* This file contains useful constants and macros for the USB applications.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BCD(x) ((((x) / 10) << 4) | ((x) / 10))
|
||||
|
||||
/* Descriptor size in bytes */
|
||||
#define USB_DEVICE_DESC_SIZE 18
|
||||
#define USB_CONFIGURATION_DESC_SIZE 9
|
||||
#define USB_INTERFACE_DESC_SIZE 9
|
||||
#define USB_ENDPOINT_DESC_SIZE 7
|
||||
#define USB_STRING_DESC_SIZE 4
|
||||
#define USB_HID_DESC_SIZE 9
|
||||
#define USB_DFU_DESC_SIZE 9
|
||||
#define USB_DEVICE_QUAL_DESC_SIZE 10
|
||||
#define USB_INTERFACE_ASSOC_DESC_SIZE 8
|
||||
|
||||
/* Descriptor type */
|
||||
#define USB_DEVICE_DESC 0x01
|
||||
#define USB_CONFIGURATION_DESC 0x02
|
||||
#define USB_STRING_DESC 0x03
|
||||
#define USB_INTERFACE_DESC 0x04
|
||||
#define USB_ENDPOINT_DESC 0x05
|
||||
#define USB_DEVICE_QUAL_DESC 0x06
|
||||
#define USB_INTERFACE_ASSOC_DESC 0x0B
|
||||
#define USB_DEVICE_CAPABILITY_DESC 0x10
|
||||
#define USB_HID_DESC 0x21
|
||||
#define USB_HID_REPORT_DESC 0x22
|
||||
#define USB_DFU_FUNCTIONAL_DESC 0x21
|
||||
#define USB_ASSOCIATION_DESC 0x0B
|
||||
#define USB_BINARY_OBJECT_STORE_DESC 0x0F
|
||||
|
||||
/* Useful define */
|
||||
#define USB_1_1 0x0110
|
||||
#define USB_2_0 0x0200
|
||||
/* Set USB version to 2.1 so that the host will request the BOS descriptor */
|
||||
#define USB_2_1 0x0210
|
||||
|
||||
#define BCDDEVICE_RELNUM (BCD(KERNEL_VERSION_MAJOR) << 8 | \
|
||||
BCD(KERNEL_VERSION_MINOR))
|
||||
|
||||
/* 100mA max power, per 2mA units */
|
||||
/* USB 1.1 spec indicates 100mA(max) per unit load, up to 5 loads */
|
||||
#define MAX_LOW_POWER 0x32
|
||||
#define MAX_HIGH_POWER 0xFA
|
||||
|
||||
/* bmAttributes:
|
||||
* D7:Reserved, always 1,
|
||||
* D6:Self-Powered -> 1,
|
||||
* D5:Remote Wakeup -> 0,
|
||||
* D4...0:Reserved -> 0
|
||||
*/
|
||||
#define USB_CONFIGURATION_ATTRIBUTES 0xC0
|
||||
|
||||
/* Classes */
|
||||
#define COMMUNICATION_DEVICE_CLASS 0x02
|
||||
#define COMMUNICATION_DEVICE_CLASS_DATA 0x0A
|
||||
#define HID_CLASS 0x03
|
||||
#define MASS_STORAGE_CLASS 0x08
|
||||
#define WIRELESS_DEVICE_CLASS 0xE0
|
||||
#define MISC_CLASS 0xEF
|
||||
#define CUSTOM_CLASS 0xFF
|
||||
#define DFU_DEVICE_CLASS 0xFE
|
||||
|
||||
/* Sub-classes */
|
||||
#define CDC_NCM_SUBCLASS 0x0d
|
||||
#define BOOT_INTERFACE_SUBCLASS 0x01
|
||||
#define SCSI_TRANSPARENT_SUBCLASS 0x06
|
||||
#define DFU_INTERFACE_SUBCLASS 0x01
|
||||
#define RF_SUBCLASS 0x01
|
||||
#define CUSTOM_SUBCLASS 0xFF
|
||||
#define COMMON_SUBCLASS 0x02
|
||||
/* Misc subclasses */
|
||||
#define MISC_RNDIS_SUBCLASS 0x04
|
||||
#define CDC_ABSTRACT_CONTROL_MODEL 0x02
|
||||
|
||||
/* Protocols */
|
||||
#define V25TER_PROTOCOL 0x01
|
||||
#define MOUSE_PROTOCOL 0x02
|
||||
#define BULK_ONLY_PROTOCOL 0x50
|
||||
#define DFU_RUNTIME_PROTOCOL 0x01
|
||||
#define DFU_MODE_PROTOCOL 0x02
|
||||
#define BLUETOOTH_PROTOCOL 0x01
|
||||
/* CDC ACM protocols */
|
||||
#define ACM_VENDOR_PROTOCOL 0xFF
|
||||
/* Misc protocols */
|
||||
#define MISC_ETHERNET_PROTOCOL 0x01
|
||||
#define IAD_PROTOCOL 0x01
|
||||
|
||||
/** Standard Device Descriptor */
|
||||
struct usb_device_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdUSB;
|
||||
uint8_t bDeviceClass;
|
||||
uint8_t bDeviceSubClass;
|
||||
uint8_t bDeviceProtocol;
|
||||
uint8_t bMaxPacketSize0;
|
||||
uint16_t idVendor;
|
||||
uint16_t idProduct;
|
||||
uint16_t bcdDevice;
|
||||
uint8_t iManufacturer;
|
||||
uint8_t iProduct;
|
||||
uint8_t iSerialNumber;
|
||||
uint8_t bNumConfigurations;
|
||||
} __packed;
|
||||
|
||||
/** Unicode (UTF16LE) String Descriptor */
|
||||
struct usb_string_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bString;
|
||||
} __packed;
|
||||
|
||||
/** Association Descriptor */
|
||||
struct usb_association_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bFirstInterface;
|
||||
uint8_t bInterfaceCount;
|
||||
uint8_t bFunctionClass;
|
||||
uint8_t bFunctionSubClass;
|
||||
uint8_t bFunctionProtocol;
|
||||
uint8_t iFunction;
|
||||
} __packed;
|
||||
|
||||
/** Standard Configuration Descriptor */
|
||||
struct usb_cfg_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wTotalLength;
|
||||
uint8_t bNumInterfaces;
|
||||
uint8_t bConfigurationValue;
|
||||
uint8_t iConfiguration;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t bMaxPower;
|
||||
} __packed;
|
||||
|
||||
/** Standard Interface Descriptor */
|
||||
struct usb_if_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bInterfaceNumber;
|
||||
uint8_t bAlternateSetting;
|
||||
uint8_t bNumEndpoints;
|
||||
uint8_t bInterfaceClass;
|
||||
uint8_t bInterfaceSubClass;
|
||||
uint8_t bInterfaceProtocol;
|
||||
uint8_t iInterface;
|
||||
} __packed;
|
||||
|
||||
/** Standard Endpoint Descriptor */
|
||||
struct usb_ep_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint16_t wMaxPacketSize;
|
||||
uint8_t bInterval;
|
||||
} __packed;
|
||||
|
||||
struct string_descriptor_zero {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wBcdLang[];
|
||||
} __packed;
|
||||
|
||||
struct string_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bString[];
|
||||
} __packed;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
413
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_dc.h
Normal file
413
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_dc.h
Normal file
@@ -0,0 +1,413 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2016 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief USB device controller APIs
|
||||
*
|
||||
* This file contains the USB device controller APIs. All device controller
|
||||
* drivers should implement the APIs described in this file.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* USB endpoint direction and number.
|
||||
*/
|
||||
|
||||
#define USB_EP_DIR_MASK 0x80
|
||||
#define USB_EP_DIR_IN 0x80
|
||||
#define USB_EP_DIR_OUT 0x00
|
||||
|
||||
/**
|
||||
* USB Driver Status Codes
|
||||
*/
|
||||
enum usb_dc_status_code {
|
||||
USB_DC_ERROR, /* USB error reported by the controller */
|
||||
USB_DC_RESET, /* USB reset */
|
||||
/* USB connection established, hardware enumeration is completed */
|
||||
USB_DC_CONNECTED,
|
||||
USB_DC_CONFIGURED, /* USB configuration done */
|
||||
USB_DC_DISCONNECTED, /* USB connection lost */
|
||||
USB_DC_SUSPEND, /* USB connection suspended by the HOST */
|
||||
USB_DC_RESUME, /* USB connection resumed by the HOST */
|
||||
USB_DC_INTERFACE, /* USB interface selected */
|
||||
USB_DC_SET_HALT, /* Set Feature ENDPOINT_HALT received */
|
||||
USB_DC_CLEAR_HALT, /* Clear Feature ENDPOINT_HALT received */
|
||||
USB_DC_UNKNOWN /* Initial USB connection status */
|
||||
};
|
||||
|
||||
/**
|
||||
* USB Endpoint Callback Status Codes
|
||||
*/
|
||||
enum usb_dc_ep_cb_status_code {
|
||||
USB_DC_EP_SETUP, /* SETUP received */
|
||||
/* Out transaction on this EP, data is available for read */
|
||||
USB_DC_EP_DATA_OUT,
|
||||
USB_DC_EP_DATA_IN, /* In transaction done on this EP */
|
||||
};
|
||||
|
||||
/**
|
||||
* USB Endpoint type
|
||||
*/
|
||||
enum usb_dc_ep_type {
|
||||
USB_DC_EP_CONTROL = 0, /* Control type endpoint */
|
||||
USB_DC_EP_ISOCHRONOUS, /* Isochronous type endpoint */
|
||||
USB_DC_EP_BULK, /* Bulk type endpoint */
|
||||
USB_DC_EP_INTERRUPT /* Interrupt type endpoint */
|
||||
};
|
||||
|
||||
/**
|
||||
* USB Endpoint Configuration.
|
||||
*/
|
||||
struct usb_dc_ep_cfg_data {
|
||||
/** The number associated with the EP in the device
|
||||
* configuration structure
|
||||
* IN EP = 0x80 | \<endpoint number\>
|
||||
* OUT EP = 0x00 | \<endpoint number\>
|
||||
*/
|
||||
uint8_t ep_addr;
|
||||
uint16_t ep_mps; /** Endpoint max packet size */
|
||||
enum usb_dc_ep_type ep_type; /** Endpoint type */
|
||||
};
|
||||
|
||||
/**
|
||||
* Callback function signature for the USB Endpoint status
|
||||
*/
|
||||
typedef void (*usb_dc_ep_callback)(uint8_t ep,
|
||||
enum usb_dc_ep_cb_status_code cb_status);
|
||||
|
||||
/**
|
||||
* Callback function signature for the device
|
||||
*/
|
||||
typedef void (*usb_dc_status_callback)(enum usb_dc_status_code cb_status,
|
||||
uint8_t *param);
|
||||
|
||||
/**
|
||||
* @brief attach USB for device connection
|
||||
*
|
||||
* Function to attach USB for device connection. Upon success, the USB PLL
|
||||
* is enabled, and the USB device is now capable of transmitting and receiving
|
||||
* on the USB bus and of generating interrupts.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_attach(void);
|
||||
|
||||
/**
|
||||
* @brief detach the USB device
|
||||
*
|
||||
* Function to detach the USB device. Upon success, the USB hardware PLL
|
||||
* is powered down and USB communication is disabled.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_detach(void);
|
||||
|
||||
/**
|
||||
* @brief reset the USB device
|
||||
*
|
||||
* This function returns the USB device and firmware back to it's initial state.
|
||||
* N.B. the USB PLL is handled by the usb_detach function
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_reset(void);
|
||||
|
||||
/**
|
||||
* @brief set USB device address
|
||||
*
|
||||
* @param[in] addr device address
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_set_address(const uint8_t addr);
|
||||
|
||||
/**
|
||||
* @brief set USB device controller status callback
|
||||
*
|
||||
* Function to set USB device controller status callback. The registered
|
||||
* callback is used to report changes in the status of the device controller.
|
||||
*
|
||||
* @param[in] cb callback function
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_set_status_callback(const usb_dc_status_callback cb);
|
||||
|
||||
/**
|
||||
* @brief check endpoint capabilities
|
||||
*
|
||||
* Function to check capabilities of an endpoint. usb_dc_ep_cfg_data structure
|
||||
* provides the endpoint configuration parameters: endpoint address,
|
||||
* endpoint maximum packet size and endpoint type.
|
||||
* The driver should check endpoint capabilities and return 0 if the
|
||||
* endpoint configuration is possible.
|
||||
*
|
||||
* @param[in] cfg Endpoint config
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data *const cfg);
|
||||
|
||||
/**
|
||||
* @brief configure endpoint
|
||||
*
|
||||
* Function to configure an endpoint. usb_dc_ep_cfg_data structure provides
|
||||
* the endpoint configuration parameters: endpoint address, endpoint maximum
|
||||
* packet size and endpoint type.
|
||||
*
|
||||
* @param[in] cfg Endpoint config
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg);
|
||||
|
||||
/**
|
||||
* @brief set stall condition for the selected endpoint
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_set_stall(const uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief clear stall condition for the selected endpoint
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_clear_stall(const uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief check if selected endpoint is stalled
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[out] stalled Endpoint stall status
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled);
|
||||
|
||||
/**
|
||||
* @brief halt the selected endpoint
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_halt(const uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief enable the selected endpoint
|
||||
*
|
||||
* Function to enable the selected endpoint. Upon success interrupts are
|
||||
* enabled for the corresponding endpoint and the endpoint is ready for
|
||||
* transmitting/receiving data.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_enable(const uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief disable the selected endpoint
|
||||
*
|
||||
* Function to disable the selected endpoint. Upon success interrupts are
|
||||
* disabled for the corresponding endpoint and the endpoint is no longer able
|
||||
* for transmitting/receiving data.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_disable(const uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief flush the selected endpoint
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_flush(const uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief write data to the specified endpoint
|
||||
*
|
||||
* This function is called to write data to the specified endpoint. The supplied
|
||||
* usb_ep_callback function will be called when data is transmitted out.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data pointer to data to write
|
||||
* @param[in] data_len length of data requested to write. This may
|
||||
* be zero for a zero length status packet.
|
||||
* @param[out] ret_bytes bytes scheduled for transmission. This value
|
||||
* may be NULL if the application expects all
|
||||
* bytes to be written
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
|
||||
const uint32_t data_len, uint32_t *const ret_bytes);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if the write to an IN endpoint (using usb_dc_ep_write) would block
|
||||
* to wait until the endpoint has enoug space
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 when writable, 0 when not, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_write_would_block(const uint8_t ep);
|
||||
|
||||
|
||||
/**
|
||||
* @brief read data from the specified endpoint
|
||||
*
|
||||
* This function is called by the Endpoint handler function, after an OUT
|
||||
* interrupt has been received for that EP. The application must only call this
|
||||
* function through the supplied usb_ep_callback function. This function clears
|
||||
* the ENDPOINT NAK, if all data in the endpoint FIFO has been read,
|
||||
* so as to accept more data from host.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data pointer to data buffer to write to
|
||||
* @param[in] max_data_len max length of data to read
|
||||
* @param[out] read_bytes Number of bytes read. If data is NULL and
|
||||
* max_data_len is 0 the number of bytes
|
||||
* available for read should be returned.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_read(const uint8_t ep, uint8_t *const data,
|
||||
const uint32_t max_data_len, uint32_t *const read_bytes);
|
||||
|
||||
/**
|
||||
* @brief set callback function for the specified endpoint
|
||||
*
|
||||
* Function to set callback function for notification of data received and
|
||||
* available to application or transmit done on the selected endpoint,
|
||||
* NULL if callback not required by application code.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] cb callback function
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb);
|
||||
|
||||
/**
|
||||
* @brief read data from the specified endpoint
|
||||
*
|
||||
* This is similar to usb_dc_ep_read, the difference being that, it doesn't
|
||||
* clear the endpoint NAKs so that the consumer is not bogged down by further
|
||||
* upcalls till he is done with the processing of the data. The caller should
|
||||
* reactivate ep by invoking usb_dc_ep_read_continue() do so.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data pointer to data buffer to write to
|
||||
* @param[in] max_data_len max length of data to read
|
||||
* @param[out] read_bytes Number of bytes read. If data is NULL and
|
||||
* max_data_len is 0 the number of bytes
|
||||
* available for read should be returned.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
|
||||
uint32_t *read_bytes);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Continue reading data from the endpoint
|
||||
*
|
||||
* Clear the endpoint NAK and enable the endpoint to accept more data
|
||||
* from the host. Usually called after usb_dc_ep_read_wait() when the consumer
|
||||
* is fine to accept more data. Thus these calls together acts as flow control
|
||||
* mechanism.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_dc_ep_read_continue(uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief Get endpoint max packet size
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return endpoint max packet size (mps)
|
||||
*/
|
||||
int usb_dc_ep_mps(uint8_t ep);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Poll for interrupts that need to be handled
|
||||
*
|
||||
* When the USB interrupt is not hooked up to an actual CPU interrupt, you
|
||||
* can call this periodically to handle the USB events that need handling.
|
||||
*/
|
||||
void usb_dc_check_poll_for_interrupts(void);
|
||||
|
||||
|
||||
/*
|
||||
* @brief Prepare for USB persist
|
||||
*
|
||||
* This takes the USB peripheral offline in such a way that it seems 'just busy' to the
|
||||
* host. This way, the chip can reboot (e.g. into bootloader mode) and pick up the USB
|
||||
* configuration again, without the connection to the host being interrupted.
|
||||
*
|
||||
* @note Actual persistence is depending on USBDC_PERSIST_ENA being set in flags, as this
|
||||
* is also used to e.g. reboot into DFU mode.
|
||||
*
|
||||
* @note Please reboot soon after calling this.
|
||||
*/
|
||||
int usb_dc_prepare_persist(void);
|
||||
|
||||
/*
|
||||
* @brief USB interrupt handler
|
||||
*
|
||||
* This can be hooked up by the OS to the USB peripheral interrupt.
|
||||
*/
|
||||
void usb_dw_isr_handler(void);
|
||||
|
||||
/**
|
||||
* @brief Provide IDF with an interface to clear the static variable usb_dw_ctrl
|
||||
*
|
||||
*
|
||||
*/
|
||||
void usb_dw_ctrl_deinit(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define USB_DESCRIPTOR_TYPE_ACM 0
|
||||
#define USB_DESCRIPTOR_TYPE_DFU 1
|
||||
|
||||
void usb_set_current_descriptor(int descriptor_type);
|
||||
|
||||
bool usb_get_descriptor(uint16_t type_index, uint16_t lang_id,
|
||||
int32_t *len, uint8_t **data);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
389
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_device.h
Normal file
389
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_device.h
Normal file
@@ -0,0 +1,389 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2006 Bertrik Sikken (bertrik@sikken.nl)
|
||||
* SPDX-FileContributor: 2016 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* LPCUSB, an USB device driver for LPC microcontrollers
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief USB device core layer APIs and structures
|
||||
*
|
||||
* This file contains the USB device core layer APIs and structures.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stddef.h>
|
||||
#include <sys/cdefs.h>
|
||||
#include "usb_dc.h"
|
||||
#include "esp_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* USB configuration
|
||||
**************************************************************************/
|
||||
|
||||
#define MAX_PACKET_SIZE0 64 /**< maximum packet size for EP 0 */
|
||||
//Note: for FS this should be 8, 16, 32, 64 bytes. HS can go up to 512.
|
||||
|
||||
/*************************************************************************
|
||||
* USB application interface
|
||||
**************************************************************************/
|
||||
|
||||
/** setup packet definitions */
|
||||
struct usb_setup_packet {
|
||||
uint8_t bmRequestType; /**< characteristics of the specific request */
|
||||
uint8_t bRequest; /**< specific request */
|
||||
uint16_t wValue; /**< request specific parameter */
|
||||
uint16_t wIndex; /**< request specific parameter */
|
||||
uint16_t wLength; /**< length of data transferred in data phase */
|
||||
} __packed;
|
||||
|
||||
|
||||
ESP_STATIC_ASSERT(sizeof(struct usb_setup_packet) == 8, "USB setup packet struct size error");
|
||||
|
||||
/**
|
||||
* Callback function signature for the device
|
||||
*/
|
||||
typedef void (*usb_status_callback)(enum usb_dc_status_code status_code,
|
||||
uint8_t *param);
|
||||
|
||||
/**
|
||||
* Callback function signature for the USB Endpoint status
|
||||
*/
|
||||
typedef void (*usb_ep_callback)(uint8_t ep,
|
||||
enum usb_dc_ep_cb_status_code cb_status);
|
||||
|
||||
/**
|
||||
* Function which handles Class specific requests corresponding to an
|
||||
* interface number specified in the device descriptor table
|
||||
*/
|
||||
typedef int (*usb_request_handler) (struct usb_setup_packet *detup,
|
||||
int32_t *transfer_len, uint8_t **payload_data);
|
||||
|
||||
/**
|
||||
* Function for interface runtime configuration
|
||||
*/
|
||||
typedef void (*usb_interface_config)(uint8_t bInterfaceNumber);
|
||||
|
||||
/*
|
||||
* USB Endpoint Configuration
|
||||
*/
|
||||
struct usb_ep_cfg_data {
|
||||
/**
|
||||
* Callback function for notification of data received and
|
||||
* available to application or transmit done, NULL if callback
|
||||
* not required by application code
|
||||
*/
|
||||
usb_ep_callback ep_cb;
|
||||
/**
|
||||
* The number associated with the EP in the device configuration
|
||||
* structure
|
||||
* IN EP = 0x80 | \<endpoint number\>
|
||||
* OUT EP = 0x00 | \<endpoint number\>
|
||||
*/
|
||||
uint8_t ep_addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* USB Interface Configuration
|
||||
*/
|
||||
struct usb_interface_cfg_data {
|
||||
/** Handler for USB Class specific Control (EP 0) communications */
|
||||
usb_request_handler class_handler;
|
||||
/** Handler for USB Vendor specific commands */
|
||||
usb_request_handler vendor_handler;
|
||||
/**
|
||||
* The custom request handler gets a first chance at handling
|
||||
* the request before it is handed over to the 'chapter 9' request
|
||||
* handler
|
||||
*/
|
||||
usb_request_handler custom_handler;
|
||||
/**
|
||||
* This data area, allocated by the application, is used to store
|
||||
* Class specific command data and must be large enough to store the
|
||||
* largest payload associated with the largest supported Class'
|
||||
* command set. This data area may be used for USB IN or OUT
|
||||
* communications
|
||||
*/
|
||||
uint8_t *payload_data;
|
||||
/**
|
||||
* This data area, allocated by the application, is used to store
|
||||
* Vendor specific payload
|
||||
*/
|
||||
uint8_t *vendor_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* @brief USB device configuration
|
||||
*
|
||||
* The Application instantiates this with given parameters added
|
||||
* using the "usb_set_config" function. Once this function is called
|
||||
* changes to this structure will result in undefined behaviour. This structure
|
||||
* may only be updated after calls to usb_deconfig
|
||||
*/
|
||||
struct usb_cfg_data {
|
||||
/**
|
||||
* USB device description, see
|
||||
* http://www.beyondlogic.org/usbnutshell/usb5.shtml#DeviceDescriptors
|
||||
*/
|
||||
const uint8_t *usb_device_description;
|
||||
/** Pointer to interface descriptor */
|
||||
const void *interface_descriptor;
|
||||
/** Function for interface runtime configuration */
|
||||
usb_interface_config interface_config;
|
||||
/** Callback to be notified on USB connection status change */
|
||||
usb_status_callback cb_usb_status;
|
||||
/** USB interface (Class) handler and storage space */
|
||||
struct usb_interface_cfg_data interface;
|
||||
/** Number of individual endpoints in the device configuration */
|
||||
uint8_t num_endpoints;
|
||||
/**
|
||||
* Pointer to an array of endpoint structs of length equal to the
|
||||
* number of EP associated with the device description,
|
||||
* not including control endpoints
|
||||
*/
|
||||
struct usb_ep_cfg_data *endpoint;
|
||||
};
|
||||
|
||||
/*
|
||||
* @brief configure USB controller
|
||||
*
|
||||
* Function to configure USB controller.
|
||||
* Configuration parameters must be valid or an error is returned
|
||||
*
|
||||
* @param[in] config Pointer to configuration structure
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_set_config(struct usb_cfg_data *config);
|
||||
|
||||
/*
|
||||
* @brief return the USB device to it's initial state
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_deconfig(void);
|
||||
|
||||
/*
|
||||
* @brief enable USB for host/device connection
|
||||
*
|
||||
* Function to enable USB for host/device connection.
|
||||
* Upon success, the USB module is no longer clock gated in hardware,
|
||||
* it is now capable of transmitting and receiving on the USB bus and
|
||||
* of generating interrupts.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_enable(struct usb_cfg_data *config);
|
||||
|
||||
/*
|
||||
* @brief disable the USB device.
|
||||
*
|
||||
* Function to disable the USB device.
|
||||
* Upon success, the specified USB interface is clock gated in hardware,
|
||||
* it is no longer capable of generating interrupts.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_disable(void);
|
||||
|
||||
/*
|
||||
* @brief Check if a write to an in ep would block until there is enough space
|
||||
* in the fifo
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one listed in the
|
||||
* device configuration table
|
||||
*
|
||||
* @return 0 if free to write, 1 if a write would block, negative errno code on fail
|
||||
*/
|
||||
int usb_write_would_block(uint8_t ep);
|
||||
|
||||
/*
|
||||
* @brief write data to the specified endpoint
|
||||
*
|
||||
* Function to write data to the specified endpoint. The supplied
|
||||
* usb_ep_callback will be called when transmission is done.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one listed in the
|
||||
* device configuration table
|
||||
* @param[in] data Pointer to data to write
|
||||
* @param[in] data_len Length of data requested to write. This may be zero for
|
||||
* a zero length status packet.
|
||||
* @param[out] bytes_ret Bytes written to the EP FIFO. This value may be NULL if
|
||||
* the application expects all bytes to be written
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_write(uint8_t ep, const uint8_t *data, uint32_t data_len,
|
||||
uint32_t *bytes_ret);
|
||||
|
||||
/*
|
||||
* @brief read data from the specified endpoint
|
||||
*
|
||||
* This function is called by the Endpoint handler function, after an
|
||||
* OUT interrupt has been received for that EP. The application must
|
||||
* only call this function through the supplied usb_ep_callback function.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one listed in
|
||||
* the device configuration table
|
||||
* @param[in] data Pointer to data buffer to write to
|
||||
* @param[in] max_data_len Max length of data to read
|
||||
* @param[out] ret_bytes Number of bytes read. If data is NULL and
|
||||
* max_data_len is 0 the number of bytes available
|
||||
* for read is returned.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_read(uint8_t ep, uint8_t *data, uint32_t max_data_len,
|
||||
uint32_t *ret_bytes);
|
||||
|
||||
/*
|
||||
* @brief set STALL condition on the specified endpoint
|
||||
*
|
||||
* This function is called by USB device class handler code to set stall
|
||||
* condition on endpoint.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one listed in
|
||||
* the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_ep_set_stall(uint8_t ep);
|
||||
|
||||
|
||||
/*
|
||||
* @brief clears STALL condition on the specified endpoint
|
||||
*
|
||||
* This function is called by USB device class handler code to clear stall
|
||||
* condition on endpoint.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one listed in
|
||||
* the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail
|
||||
*/
|
||||
int usb_ep_clear_stall(uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief read data from the specified endpoint
|
||||
*
|
||||
* This is similar to usb_ep_read, the difference being that, it doesn't
|
||||
* clear the endpoint NAKs so that the consumer is not bogged down by further
|
||||
* upcalls till he is done with the processing of the data. The caller should
|
||||
* reactivate ep by invoking usb_ep_read_continue() do so.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data pointer to data buffer to write to
|
||||
* @param[in] max_data_len max length of data to read
|
||||
* @param[out] read_bytes Number of bytes read. If data is NULL and
|
||||
* max_data_len is 0 the number of bytes
|
||||
* available for read should be returned.
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
|
||||
uint32_t *read_bytes);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Continue reading data from the endpoint
|
||||
*
|
||||
* Clear the endpoint NAK and enable the endpoint to accept more data
|
||||
* from the host. Usually called after usb_ep_read_wait() when the consumer
|
||||
* is fine to accept more data. Thus these calls together acts as flow control
|
||||
* mechanism.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_ep_read_continue(uint8_t ep);
|
||||
|
||||
/**
|
||||
* Callback function signature for transfer completion.
|
||||
*/
|
||||
typedef void (*usb_transfer_callback)(uint8_t ep, int tsize, void *priv);
|
||||
|
||||
/* USB transfer flags */
|
||||
#define USB_TRANS_READ BIT(0) /** Read transfer flag */
|
||||
#define USB_TRANS_WRITE BIT(1) /** Write transfer flag */
|
||||
#define USB_TRANS_NO_ZLP BIT(2) /** No zero-length packet flag */
|
||||
|
||||
/**
|
||||
* @brief Transfer management endpoint callback
|
||||
*
|
||||
* If a USB class driver wants to use high-level transfer functions, driver
|
||||
* needs to register this callback as usb endpoint callback.
|
||||
*/
|
||||
void usb_transfer_ep_callback(uint8_t ep, enum usb_dc_ep_cb_status_code);
|
||||
|
||||
/**
|
||||
* @brief Start a transfer
|
||||
*
|
||||
* Start a usb transfer to/from the data buffer. This function is asynchronous
|
||||
* and can be executed in IRQ context. The provided callback will be called
|
||||
* on transfer completion (or error) in thread context.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data Pointer to data buffer to write-to/read-from
|
||||
* @param[in] dlen Size of data buffer
|
||||
* @param[in] flags Transfer flags (USB_TRANS_READ, USB_TRANS_WRITE...)
|
||||
* @param[in] cb Function called on transfer completion/failure
|
||||
* @param[in] priv Data passed back to the transfer completion callback
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_transfer(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags,
|
||||
usb_transfer_callback cb, void *priv);
|
||||
|
||||
/**
|
||||
* @brief Start a transfer and block-wait for completion
|
||||
*
|
||||
* Synchronous version of usb_transfer, wait for transfer completion before
|
||||
* returning.
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data Pointer to data buffer to write-to/read-from
|
||||
* @param[in] dlen Size of data buffer
|
||||
* @param[in] flags Transfer flags
|
||||
|
||||
*
|
||||
* @return number of bytes transferred on success, negative errno code on fail.
|
||||
*/
|
||||
int usb_transfer_sync(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags);
|
||||
|
||||
/**
|
||||
* @brief Cancel any ongoing transfer on the specified endpoint
|
||||
*
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
void usb_cancel_transfer(uint8_t ep);
|
||||
|
||||
/**
|
||||
* @brief Provide IDF with an interface to clear the static variable usb_dev
|
||||
*
|
||||
*
|
||||
*/
|
||||
void usb_dev_deinit(void);
|
||||
|
||||
void usb_dev_resume(int configuration);
|
||||
int usb_dev_get_configuration(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
122
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_dfu.h
Normal file
122
components/esp_rom/esp32s3/include/esp32s3/rom/usb/usb_dfu.h
Normal file
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015,2016 Intel Corporation
|
||||
* SPDX-FileContributor: 2017 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief USB Device Firmware Upgrade (DFU) public header
|
||||
*
|
||||
* Header follows the Device Class Specification for
|
||||
* Device Firmware Upgrade Version 1.1
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "usb_device.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** DFU Class Subclass */
|
||||
#define DFU_SUBCLASS 0x01
|
||||
|
||||
/** DFU Class runtime Protocol */
|
||||
#define DFU_RT_PROTOCOL 0x01
|
||||
|
||||
/** DFU Class DFU mode Protocol */
|
||||
#define DFU_MODE_PROTOCOL 0x02
|
||||
|
||||
/**
|
||||
* @brief DFU Class Specific Requests
|
||||
*/
|
||||
#define DFU_DETACH 0x00
|
||||
#define DFU_DNLOAD 0x01
|
||||
#define DFU_UPLOAD 0x02
|
||||
#define DFU_GETSTATUS 0x03
|
||||
#define DFU_CLRSTATUS 0x04
|
||||
#define DFU_GETSTATE 0x05
|
||||
#define DFU_ABORT 0x06
|
||||
|
||||
/** DFU FUNCTIONAL descriptor type */
|
||||
#define DFU_FUNC_DESC 0x21
|
||||
|
||||
/** DFU attributes DFU Functional Descriptor */
|
||||
#define DFU_ATTR_WILL_DETACH 0x08
|
||||
#define DFU_ATTR_MANIFESTATION_TOLERANT 0x04
|
||||
#define DFU_ATTR_CAN_UPLOAD 0x02
|
||||
#define DFU_ATTR_CAN_DNLOAD 0x01
|
||||
|
||||
/** DFU Specification release */
|
||||
#define DFU_VERSION 0x0110
|
||||
|
||||
/** Run-Time Functional Descriptor */
|
||||
struct dfu_runtime_descriptor {
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bmAttributes;
|
||||
uint16_t wDetachTimeOut;
|
||||
uint16_t wTransferSize;
|
||||
uint16_t bcdDFUVersion;
|
||||
} __packed;
|
||||
|
||||
/** bStatus values for the DFU_GETSTATUS response */
|
||||
enum dfu_status {
|
||||
statusOK,
|
||||
errTARGET,
|
||||
errFILE,
|
||||
errWRITE,
|
||||
errERASE,
|
||||
errCHECK_ERASED,
|
||||
errPROG,
|
||||
errVERIFY,
|
||||
errADDRESS,
|
||||
errNOTDONE,
|
||||
errFIRMWARE,
|
||||
errVENDOR,
|
||||
errUSB,
|
||||
errPOR,
|
||||
errUNKNOWN,
|
||||
errSTALLEDPKT
|
||||
};
|
||||
|
||||
/** bState values for the DFU_GETSTATUS response */
|
||||
enum dfu_state {
|
||||
appIDLE,
|
||||
appDETACH,
|
||||
dfuIDLE,
|
||||
dfuDNLOAD_SYNC,
|
||||
dfuDNBUSY,
|
||||
dfuDNLOAD_IDLE,
|
||||
dfuMANIFEST_SYNC,
|
||||
dfuMANIFEST,
|
||||
dfuMANIFEST_WAIT_RST,
|
||||
dfuUPLOAD_IDLE,
|
||||
dfuERROR,
|
||||
};
|
||||
|
||||
/*
|
||||
These callbacks are made public so the ACM driver can call them to handle the switch to DFU.
|
||||
*/
|
||||
|
||||
int dfu_class_handle_req(struct usb_setup_packet *pSetup,
|
||||
int32_t *data_len, uint8_t **data);
|
||||
void dfu_status_cb(enum usb_dc_status_code status, uint8_t *param);
|
||||
int usb_dfu_init(void);
|
||||
int dfu_custom_handle_req(struct usb_setup_packet *pSetup,
|
||||
int32_t *data_len, uint8_t **data);
|
||||
|
||||
|
||||
typedef void(*usb_dfu_detach_routine_t)(int delay);
|
||||
void usb_dfu_set_detach_cb(usb_dfu_detach_routine_t cb);
|
||||
void usb_dfu_force_detach(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
typedef void(*usb_osglue_intdisena_routine_t)(void);
|
||||
typedef int(*usb_osglue_wait_routine_t)(int delay_us);
|
||||
|
||||
typedef struct {
|
||||
/* Disable USB interrupt */
|
||||
usb_osglue_intdisena_routine_t int_dis_proc;
|
||||
/* Enable USB interrupt */
|
||||
usb_osglue_intdisena_routine_t int_ena_proc;
|
||||
/* Wait for a set amount of uS. Return the amount actually waited. If delay_us is 0, just yield.*/
|
||||
usb_osglue_wait_routine_t wait_proc;
|
||||
} usb_osglue_data_t;
|
||||
|
||||
extern usb_osglue_data_t rom_usb_osglue;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// USB persistence flags.
|
||||
|
||||
//This bit indicates persistence has been enabled, that is, the USB initialization routines should not
|
||||
//reset the USB device as the device still is initialized and the host detected it with the same cdcacm/dfu
|
||||
//descriptor as the ROM uses; we can just re-initialize the software side and have at 'er.
|
||||
#define USBDC_PERSIST_ENA (1<<31)
|
||||
|
||||
//This bit indicates to the ROM that we rebooted because of a request to go into DFU mode; the ROM should
|
||||
//honour this request.
|
||||
#define USBDC_BOOT_DFU (1<<30)
|
||||
|
||||
|
||||
//This being non-0 indicates a memory location where a 'testament' is stored, aka a piece of text that should be output
|
||||
//after a reboot. Can contain core dump info or something.
|
||||
#define USBDC_TESTAMENT_LOC_MASK 0x7FFFF //bits 19-0; this is added to a base address of SOC_MEM_INTERNAL_LOW. (0x3FF9E000)
|
||||
|
||||
//The testament is a FIFO. The ROM will output all data between textstart and textend; if textend is lower than textstart it will
|
||||
//output everything from textstart to memend, then memstart to textend.
|
||||
typedef struct {
|
||||
char *memstart; //start of memory region
|
||||
char *memend; //end of memory region
|
||||
char *textstart; //start of text to output
|
||||
char *textend;
|
||||
} usbdc_testament_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user