intr_alloc: split interrupt allocator into common-code and platform-code

esp_system: removed repeated interrupt allocator code and moved common code to esp_system

xtens: moved xtensa specific code from freertos to the xtensa component

hal/interrupt_controller: added interrupt controller hal and ll files

docs: update the doxyfile with new location of esp_itr_alloc.h file

xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos

docs: removed Xtensa reference from intr_allocator api-reference

xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer

esp_system/test: fixed platform dependent setting for intr_allocator tests

hal: rename the functions used to manage non iram interrupt mask.

components/hal/esp32s2/include/hal/interrupt_controller_ll.h

@@ -0,0 +1,105 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once 
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+#include "soc/soc.h"
+#include "xtensa/xtensa_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief enable interrupts specified by the mask
+ * 
+ * @param mask bitmask of interrupts that needs to be enabled 
+ */
+static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask) 
+{
+    xt_ints_on(mask);
+}
+
+/**
+ * @brief disable interrupts specified by the mask
+ * 
+ * @param mask bitmask of interrupts that needs to be disabled 
+ */
+static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
+{
+    xt_ints_off(mask);
+}
+
+/**
+ * @brief checks if given interrupt number has a valid handler
+ * 
+ * @param intr interrupt number ranged from 0 to 31
+ * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
+ * @return true for valid handler, false otherwise 
+ */
+static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
+{
+    return xt_int_has_handler(intr, cpu);
+}
+
+/**
+ * @brief sets interrupt handler and optional argument of a given interrupt number 
+ * 
+ * @param intr interrupt number ranged from 0 to 31
+ * @param handler handler invoked when an interrupt occurs
+ * @param arg optional argument to pass to the handler
+ */
+static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
+{
+    xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
+}
+
+/**
+ * @brief Gets argument passed to handler of a given interrupt number 
+ * 
+ * @param intr interrupt number ranged from 0 to 31
+ * 
+ * @return argument used by handler of passed interrupt number
+ */
+static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
+{
+    return xt_get_interrupt_handler_arg(intr);
+}
+
+/**
+ * @brief Disables interrupts that are not located in iram
+ * 
+ * @param newmask mask of interrupts needs to be disabled
+ * @return oldmask where to store old interrupts state
+ */
+static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask) 
+{
+    return xt_int_disable_mask(newmask);
+}
+
+/**
+ * @brief Enables interrupts that are not located in iram
+ * 
+ * @param newmask mask of interrupts needs to be disabled
+ */
+static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
+{
+    xt_int_enable_mask(newmask);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32s2/interrupt_descriptor_table.c

@@ -0,0 +1,75 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "sdkconfig.h"
+#include "hal/interrupt_controller_hal.h"
+#include "hal/interrupt_controller_ll.h"
+#include "soc/soc_caps.h"
+#include "soc/soc.h"
+
+//We should mark the interrupt for the timer used by FreeRTOS as reserved. The specific timer
+//is selectable using menuconfig; we use these cpp bits to convert that into something we can use in
+//the table below.
+#if CONFIG_FREERTOS_CORETIMER_0
+#define INT6RES INTDESC_RESVD
+#else
+#define INT6RES INTDESC_SPECIAL
+#endif
+
+#if CONFIG_FREERTOS_CORETIMER_1
+#define INT15RES INTDESC_RESVD
+#else
+#define INT15RES INTDESC_SPECIAL
+#endif
+
+//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
+const static int_desc_t interrupt_descriptor_table [32]={
+    { 1, INTTP_LEVEL, {INTDESC_RESVD} }, //0
+    { 1, INTTP_LEVEL, {INTDESC_RESVD} }, //1
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL} }, //2
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL} }, //3
+    { 1, INTTP_LEVEL, {INTDESC_RESVD} }, //4
+    { 1, INTTP_LEVEL, {INTDESC_RESVD} }, //5
+    { 1, INTTP_NA,    {INT6RES} }, //6
+    { 1, INTTP_NA,    {INTDESC_SPECIAL}}, //7
+    { 1, INTTP_LEVEL, {INTDESC_RESVD } }, //8
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //9
+    { 1, INTTP_EDGE , {INTDESC_NORMAL } }, //10
+    { 3, INTTP_NA,    {INTDESC_SPECIAL }}, //11
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //12
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL} }, //13
+    { 7, INTTP_LEVEL, {INTDESC_RESVD} }, //14, NMI
+    { 3, INTTP_NA,    {INT15RES} }, //15
+    { 5, INTTP_NA,    {INTDESC_SPECIAL } }, //16
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //17
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //18
+    { 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //19
+    { 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //20
+    { 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //21
+    { 3, INTTP_EDGE,  {INTDESC_RESVD } }, //22
+    { 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //23
+    { 4, INTTP_LEVEL, {INTDESC_RESVD } }, //24
+    { 4, INTTP_LEVEL, {INTDESC_RESVD } }, //25
+    { 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //26
+    { 3, INTTP_LEVEL, {INTDESC_RESVD } }, //27
+    { 4, INTTP_EDGE,  {INTDESC_NORMAL } }, //28
+    { 3, INTTP_NA,    {INTDESC_SPECIAL }}, //29
+    { 4, INTTP_EDGE,  {INTDESC_RESVD } }, //30
+    { 5, INTTP_LEVEL, {INTDESC_RESVD } }, //31
+};
+
+const int_desc_t *interrupt_controller_hal_desc_table(void) 
+{
+    return interrupt_descriptor_table;
+}