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refactor(spi_flash): Use new spi_flash register sturct and deperecate the old one

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This commit is contained in:
Cao Sen Miao
2024-01-04 10:24:17 +08:00
parent 8325b507e0
commit 2e83fa1c69
28 changed files with 663 additions and 5241 deletions
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22
components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,7 +15,7 @@
#include <stdbool.h>
#include <string.h>
#include "soc/hp_system_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/spi_mem_c_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
@@ -61,7 +61,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_SPI_XTS_DESTINATION, type);
REG_SET_FIELD(SPI_MEM_C_XTS_DESTINATION_REG, SPI_MEM_C_XTS_DESTINATION, type);
}
/**
@@ -72,7 +72,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
// Desired block should not be larger than the block size.
REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_SPI_XTS_LINESIZE, size >> 5);
REG_SET_FIELD(SPI_MEM_C_XTS_LINESIZE_REG, SPI_MEM_C_XTS_LINESIZE, size >> 5);
}
/**
@@ -87,7 +87,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
{
uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
memcpy((void *)(SPI_MEM_C_XTS_PLAIN_BASE_REG + plaintext_offs), buffer, size);
}
/**
@@ -97,7 +97,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
REG_SET_FIELD(SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG, SPI_MEM_C_XTS_PHYSICAL_ADDRESS, flash_addr);
}
/**
@@ -105,7 +105,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_SPI_XTS_TRIGGER, 1);
REG_SET_FIELD(SPI_MEM_C_XTS_TRIGGER_REG, SPI_XTS_TRIGGER, 1);
}
/**
@@ -113,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) == 0x1) {
while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) == 0x1) {
}
}
@@ -122,8 +122,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_SPI_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) != 0x3) {
REG_SET_BIT(SPI_MEM_C_XTS_RELEASE_REG, SPI_MEM_C_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) != 0x3) {
}
}
@@ -132,7 +132,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_SPI_XTS_DESTROY);
REG_SET_BIT(SPI_MEM_C_XTS_DESTROY_REG, SPI_MEM_C_XTS_DESTROY);
}
/**

1
components/hal/esp32p4/include/hal/spi_flash_ll.h
View File

@@ -92,6 +92,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

43
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,7 +20,8 @@
#include <string.h>
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
#include "soc/spi1_mem_c_struct.h"
#include "soc/spi1_mem_c_reg.h"
#include "hal/assert.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
@@ -208,7 +209,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
*/
static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
{
dev->flash_sus_ctrl.frd_sus_2b = 0;
dev->flash_sus_ctrl.fmem_rd_sus_2b = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
}
@@ -454,8 +455,8 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
{
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
ctrl.val &= ~(SPI1_MEM_C_FREAD_QIO_M | SPI1_MEM_C_FREAD_QUAD_M | SPI1_MEM_C_FREAD_DIO_M | SPI1_MEM_C_FREAD_DUAL_M);
ctrl.val |= SPI1_MEM_C_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
@@ -565,7 +566,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.usr_addr_4byte = 0;
dev->cache_fctrl.cache_usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
}
@@ -612,10 +613,7 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
if (hold_n > 0) {
dev->ctrl2.cs_hold_time = hold_n - 1;
}
dev->user.cs_hold = hold_n > 0;
// Not supported on esp32p4
}
/**
@@ -626,10 +624,7 @@ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
*/
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
{
if (cs_setup_time > 0) {
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
}
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
// Not supported on esp32p4
}
/**
@@ -664,6 +659,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp_reg = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif