ulp: refactor ulp component

This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.

This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.

components/ulp/ulp_common/include/esp32/ulp_common_defs.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __ULP_COMMON_DEFS_H__
+#define __ULP_COMMON_DEFS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTC_SLOW_MEM ((uint32_t*) 0x50000000)       /*!< RTC slow memory, 8k size */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ULP_COMMON_DEFS_H__

components/ulp/ulp_common/include/esp32s2/ulp_common_defs.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __ULP_COMMON_DEFS_H__
+#define __ULP_COMMON_DEFS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTC_SLOW_MEM ((uint32_t*) 0x50000000)       /*!< RTC slow memory, 8k size */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ULP_COMMON_DEFS_H__

components/ulp/ulp_common/include/esp32s3/ulp_common_defs.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __ULP_COMMON_DEFS_H__
+#define __ULP_COMMON_DEFS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTC_SLOW_MEM ((uint32_t*) 0x50000000)       /*!< RTC slow memory, 8k size */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ULP_COMMON_DEFS_H__

components/ulp/ulp_common/include/ulp_common.h

@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __ULP_COMMON_H__
+#define __ULP_COMMON_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "ulp_common_defs.h"
+
+/**
+ * @brief Set one of ULP wakeup period values
+ *
+ * ULP coprocessor starts running the program when the wakeup timer counts up
+ * to a given value (called period). There are 5 period values which can be
+ * programmed into SENS_ULP_CP_SLEEP_CYCx_REG registers, x = 0..4 for ESP32, and
+ * one period value which can be programmed into RTC_CNTL_ULP_CP_TIMER_1_REG register for ESP32-S2/S3.
+ * By default, for ESP32, wakeup timer will use the period set into SENS_ULP_CP_SLEEP_CYC0_REG,
+ * i.e. period number 0. ULP program code can use SLEEP instruction to select
+ * which of the SENS_ULP_CP_SLEEP_CYCx_REG should be used for subsequent wakeups.
+ *
+ * However, please note that SLEEP instruction issued (from ULP program) while the system
+ * is in deep sleep mode does not have effect, and sleep cycle count 0 is used.
+ *
+ * For ESP32-S2/S3 the SLEEP instruction not exist. Instead a WAKE instruction will be used.
+ *
+ * @param period_index wakeup period setting number (0 - 4)
+ * @param period_us wakeup period, us
+ * @note  The ULP FSM requires two clock cycles to wakeup before being able to run the program.
+ *        Then additional 16 cycles are reserved after wakeup waiting until the 8M clock is stable.
+ *        The FSM also requires two more clock cycles to go to sleep after the program execution is halted.
+ *        The minimum wakeup period that may be set up for the ULP
+ *        is equal to the total number of cycles spent on the above internal tasks.
+ *        For a default configuration of the ULP running at 150kHz it makes about 133us.
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if period_index is out of range
+ */
+esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ULP_COMMON_H__

components/ulp/ulp_common/ulp_common.c

@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include "esp_err.h"
+#include "esp_log.h"
+#include "ulp_common.h"
+#include "esp_private/esp_clk.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/sens_reg.h"
+
+#if CONFIG_IDF_TARGET_ESP32
+#define ULP_FSM_PREPARE_SLEEP_CYCLES 2    /*!< Cycles spent by FSM preparing ULP for sleep */
+#define ULP_FSM_WAKEUP_SLEEP_CYCLES  2    /*!< Cycles spent by FSM waking up ULP from sleep */
+#endif
+
+esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
+{
+    if (period_index > 4) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    uint64_t period_us_64 = period_us;
+
+#if CONFIG_IDF_TARGET_ESP32
+    uint64_t period_cycles = (period_us_64 << RTC_CLK_CAL_FRACT) / esp_clk_slowclk_cal_get();
+    uint64_t min_sleep_period_cycles = ULP_FSM_PREPARE_SLEEP_CYCLES
+                                    + ULP_FSM_WAKEUP_SLEEP_CYCLES
+                                    + REG_GET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT);
+    if (period_cycles < min_sleep_period_cycles) {
+        period_cycles = min_sleep_period_cycles;
+        ESP_LOGW("ulp", "Sleep period clipped to minimum of %d cycles", (uint32_t) min_sleep_period_cycles);
+    } else {
+        period_cycles -= min_sleep_period_cycles;
+    }
+    REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t),
+            SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles);
+#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
+    rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
+    rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
+    rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
+    rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
+    if (slow_clk_freq == (rtc_slow_freq_x32k)) {
+        cal_clk = RTC_CAL_32K_XTAL;
+    } else if (slow_clk_freq == rtc_slow_freq_8MD256) {
+        cal_clk  = RTC_CAL_8MD256;
+    }
+    uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
+    uint64_t period_cycles = rtc_time_us_to_slowclk(period_us_64, slow_clk_period);
+
+    REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_1_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, ((uint32_t)period_cycles));
+#endif
+    return ESP_OK;
+}