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feature(I2S-ADC): add ADC mode for I2S.

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1. Support built-in ADC for I2S.
2. Modify code of ADC, made no change to the original APIs.
3. Add APIs in I2S:
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
4. Add I2S ADC/DAC example code.
5. add old-fashion definition to make it more compatible
6. replase spi_flash_ APIs with esp_partition_ APIs
7. add example of generating audio table from wav
8. change example sound
This commit is contained in:
Wangjialin
2017-08-23 23:12:56 +08:00
parent b2adaf2a4c
commit 2fceec4d85
24 changed files with 6242 additions and 162 deletions
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2
components/soc/esp32/include/soc/sens_reg.h
View File

@@ -297,6 +297,8 @@
#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S))
#define SENS_SAR1_ATTEN_V 0xFFFFFFFF
#define SENS_SAR1_ATTEN_S 0
#define SENS_SAR1_ATTEN_VAL_MASK 0x3
#define SENS_SAR2_ATTEN_VAL_MASK 0x3
#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038)
/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */

136
components/soc/esp32/include/soc/syscon_struct.h
View File

@@ -18,112 +18,106 @@
extern "C" {
#endif
typedef struct {
typedef volatile struct {
union {
struct {
volatile uint32_t pre_div: 10;
volatile uint32_t clk_320m_en: 1;
volatile uint32_t clk_en: 1;
volatile uint32_t rst_tick: 1;
volatile uint32_t quick_clk_chng: 1;
volatile uint32_t reserved14: 18;
uint32_t pre_div: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick: 1;
uint32_t quick_clk_chng: 1;
uint32_t reserved14: 18;
};
volatile uint32_t val;
uint32_t val;
}clk_conf;
union {
struct {
volatile uint32_t xtal_tick: 8;
volatile uint32_t reserved8: 24;
uint32_t xtal_tick: 8;
uint32_t reserved8: 24;
};
volatile uint32_t val;
uint32_t val;
}xtal_tick_conf;
union {
struct {
volatile uint32_t pll_tick: 8;
volatile uint32_t reserved8: 24;
uint32_t pll_tick: 8;
uint32_t reserved8: 24;
};
volatile uint32_t val;
uint32_t val;
}pll_tick_conf;
union {
struct {
volatile uint32_t ck8m_tick: 8;
volatile uint32_t reserved8: 24;
uint32_t ck8m_tick: 8;
uint32_t reserved8: 24;
};
volatile uint32_t val;
uint32_t val;
}ck8m_tick_conf;
union {
struct {
volatile uint32_t start_force: 1;
volatile uint32_t start: 1;
volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/
volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
volatile uint32_t sar_clk_gated: 1;
volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/
volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
volatile uint32_t reserved27: 5;
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t reserved27: 5;
};
volatile uint32_t val;
uint32_t val;
}saradc_ctrl;
union {
struct {
volatile uint32_t meas_num_limit: 1;
volatile uint32_t max_meas_num: 8; /*max conversion number*/
volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
volatile uint32_t reserved11: 21;
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t reserved11: 21;
};
volatile uint32_t val;
uint32_t val;
}saradc_ctrl2;
union {
struct {
volatile uint32_t rstb_wait: 8;
volatile uint32_t standby_wait: 8;
volatile uint32_t start_wait: 8;
volatile uint32_t sample_cycle: 8; /*sample cycles*/
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t start_wait: 8;
uint32_t sample_cycle: 8; /*sample cycles*/
};
volatile uint32_t val;
uint32_t val;
}saradc_fsm;
volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 3 for ADC1 pattern table*/
uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 3 for ADC2 pattern table*/
union {
struct {
volatile uint32_t apll_tick: 8;
volatile uint32_t reserved8: 24;
uint32_t apll_tick: 8;
uint32_t reserved8: 24;
};
volatile uint32_t val;
uint32_t val;
}apll_tick_conf;
volatile uint32_t reserved_40;
volatile uint32_t reserved_44;
volatile uint32_t reserved_48;
volatile uint32_t reserved_4c;
volatile uint32_t reserved_50;
volatile uint32_t reserved_54;
volatile uint32_t reserved_58;
volatile uint32_t reserved_5c;
volatile uint32_t reserved_60;
volatile uint32_t reserved_64;
volatile uint32_t reserved_68;
volatile uint32_t reserved_6c;
volatile uint32_t reserved_70;
volatile uint32_t reserved_74;
volatile uint32_t reserved_78;
volatile uint32_t date; /**/
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t date; /**/
} syscon_dev_t;
#ifdef __cplusplus
}
#endif
extern syscon_dev_t SYSCON;
#endif /* _SOC_SYSCON_STRUCT_H_ */