mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-09 12:35:28 +00:00
I2C: Refactor i2c hal and ll
This commit is contained in:
Cao Sen Miao
@@ -7,16 +7,18 @@
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// The LL layer for I2C register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/i2c_periph.h"
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#include "soc/i2c_struct.h"
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#include "soc/clk_tree_defs.h"
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#include "hal/i2c_types.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I2C_LL_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */
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/**
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* @brief I2C hardware cmd register fields.
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@@ -34,34 +36,6 @@ typedef union {
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uint32_t val;
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} i2c_hw_cmd_t;
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/**
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* @brief I2C interrupt event
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*/
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typedef enum {
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I2C_INTR_EVENT_ERR,
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I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */
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I2C_INTR_EVENT_NACK, /*!< I2C NACK event */
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I2C_INTR_EVENT_TOUT, /*!< I2C time out event */
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I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */
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I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */
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I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */
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I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */
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} i2c_intr_event_t;
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/**
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* @brief Data structure for calculating I2C bus timing.
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*/
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typedef struct {
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uint16_t scl_low; /*!< I2C scl low period */
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uint16_t scl_high; /*!< I2C scl hight period */
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uint16_t scl_wait_high; /*!< I2C scl wait_high period */
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uint16_t sda_hold; /*!< I2C scl low period */
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uint16_t sda_sample; /*!< I2C sda sample time */
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uint16_t setup; /*!< I2C start and stop condition setup period */
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uint16_t hold; /*!< I2C start and stop condition hold period */
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uint16_t tout; /*!< I2C bus timeout period */
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} i2c_clk_cal_t;
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// I2C operation mode command
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#define I2C_LL_CMD_RESTART 0 /*!<I2C restart command */
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#define I2C_LL_CMD_WRITE 1 /*!<I2C write command */
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@@ -69,20 +43,26 @@ typedef struct {
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#define I2C_LL_CMD_STOP 3 /*!<I2C stop command */
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#define I2C_LL_CMD_END 4 /*!<I2C end command */
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// Get the I2C hardware instance
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#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == 0) ? &I2C0 : &I2C1)
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// Get the I2C hardware FIFO address
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#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num))
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// I2C master TX interrupt bitmap
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#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
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// I2C master RX interrupt bitmap
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#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
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// I2C slave TX interrupt bitmap
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#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M)
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// I2C slave RX interrupt bitmap
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#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
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// I2C max timeout value
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#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V
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typedef enum {
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I2C_INTR_NACK = (1 << 10),
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I2C_INTR_TIMEOUT = (1 << 8),
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I2C_INTR_MST_COMPLETE = (1 << 7),
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I2C_INTR_ARBITRATION = (1 << 5),
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I2C_INTR_END_DETECT = (1 << 3),
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I2C_INTR_ST_TO = (1 << 13),
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} i2c_ll_master_intr_t;
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typedef enum {
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I2C_INTR_TXFIFO_WM = (1 << 1),
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I2C_INTR_RXFIFO_WM = (1 << 0),
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I2C_INTR_SLV_COMPLETE = (1 << 7),
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I2C_INTR_START = (1 << 15),
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} i2c_ll_slave_intr_t;
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#define I2C_LL_MASTER_EVENT_INTR (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
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#define I2C_LL_SLAVE_EVENT_INTR (I2C_RXFIFO_WM_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_TXFIFO_WM_INT_ENA_M)
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/**
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* @brief Calculate I2C bus frequency
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*
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@@ -92,7 +72,7 @@ typedef struct {
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*
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* @return None
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*/
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static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_clk_cal_t *clk_cal)
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static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal)
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{
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uint32_t half_cycle = source_clk / bus_freq / 2;
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//SCL
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@@ -117,7 +97,7 @@ static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2
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*
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* @return None
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*/
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static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
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static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg)
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{
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//scl period
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hw->scl_low_period.period = bus_cfg->scl_low - 1;
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@@ -185,7 +165,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
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*
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* @return None
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*/
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static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask)
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__attribute__((always_inline))
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static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask)
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{
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hw->int_clr.val = mask;
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}
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@@ -211,6 +192,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val &= (~mask);
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@@ -223,9 +205,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask)
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*
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* @return I2C interrupt status
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*/
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static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw)
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__attribute__((always_inline))
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static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
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{
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return hw->int_status.val;
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*intr_status = hw->int_status.val;
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}
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/**
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@@ -443,9 +426,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw)
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*
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* @return RxFIFO readable length
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*/
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static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
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__attribute__((always_inline))
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static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
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{
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return hw->status_reg.rx_fifo_cnt;
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*length = hw->status_reg.rx_fifo_cnt;
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}
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/**
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@@ -455,9 +439,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
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*
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* @return TxFIFO writable length
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*/
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static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
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__attribute__((always_inline))
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static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
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{
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return SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt;
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*length = SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt;
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}
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/**
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@@ -467,9 +452,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
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*
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* @return The I2C timeout value
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*/
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static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw)
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static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
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{
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return hw->timeout.tout;
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*timeout = hw->timeout.tout;
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}
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/**
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@@ -538,7 +523,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
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*
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* @return None.
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*/
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static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
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__attribute__((always_inline))
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static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
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{
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uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
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for(int i = 0; i < len; i++) {
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@@ -555,6 +541,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
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{
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uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
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@@ -592,155 +579,9 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
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*
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* @return The hardware filter configuration
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*/
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static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw)
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static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
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{
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return hw->sda_filter_cfg.thres;
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}
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/**
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* @brief Enable I2C master TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = ~0;
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hw->int_ena.val = I2C_LL_MASTER_TX_INT;
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}
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/**
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* @brief Enable I2C master RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = ~0;
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hw->int_ena.val = I2C_LL_MASTER_RX_INT;
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}
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/**
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* @brief Disable I2C master TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
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}
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/**
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* @brief Disable I2C master RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT);
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}
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/**
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* @brief Clear I2C master TX interrupt status register
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = I2C_LL_MASTER_TX_INT;
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}
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/**
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* @brief Clear I2C master RX interrupt status register
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = I2C_LL_MASTER_RX_INT;
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}
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/**
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* @brief Enable I2C slave TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val |= I2C_LL_SLAVE_TX_INT;
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}
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/**
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* @brief Enable I2C slave RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val |= I2C_LL_SLAVE_RX_INT;
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}
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/**
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* @brief Disable I2C slave TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT);
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}
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/**
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* @brief Disable I2C slave RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT);
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}
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/**
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* @brief Clear I2C slave TX interrupt status register
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = I2C_LL_SLAVE_TX_INT;
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}
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/**
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* @brief Clear I2C slave RX interrupt status register.
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = I2C_LL_SLAVE_RX_INT;
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*filter_conf = hw->sda_filter_cfg.thres;
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}
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/**
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@@ -786,53 +627,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c
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hw->ctr.ref_always_on = (src_clk == I2C_CLK_SRC_REF_TICK) ? 0 : 1;
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}
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/**
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* @brief Get I2C master interrupt event
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*
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* @param hw Beginning address of the peripheral registers
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* @param event Pointer to accept the interrupt event
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*
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* @return None
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*/
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static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
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{
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typeof(hw->int_status) int_sts = hw->int_status;
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if (int_sts.arbitration_lost) {
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*event = I2C_INTR_EVENT_ARBIT_LOST;
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} else if (int_sts.nack) {
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*event = I2C_INTR_EVENT_NACK;
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} else if (int_sts.time_out) {
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*event = I2C_INTR_EVENT_TOUT;
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} else if (int_sts.end_detect) {
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*event = I2C_INTR_EVENT_END_DET;
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} else if (int_sts.trans_complete) {
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*event = I2C_INTR_EVENT_TRANS_DONE;
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} else {
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*event = I2C_INTR_EVENT_ERR;
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}
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}
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/**
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* @brief Get I2C slave interrupt event
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*
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* @param hw Beginning address of the peripheral registers
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* @param event Pointer to accept the interrupt event
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*
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* @return None
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*/
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static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
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{
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typeof(hw->int_status) int_sts = hw->int_status;
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if (int_sts.tx_fifo_wm) {
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*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
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} else if (int_sts.trans_complete) {
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*event = I2C_INTR_EVENT_TRANS_DONE;
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} else if (int_sts.rx_fifo_wm) {
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*event = I2C_INTR_EVENT_RXFIFO_FULL;
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} else {
|
||||
*event = I2C_INTR_EVENT_ERR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Init I2C master
|
||||
@@ -893,11 +687,67 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void i2c_ll_update(i2c_dev_t *hw)
|
||||
{
|
||||
;// ESP32S2 do not support
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set whether slave should auto start, or only start with start signal from master
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
|
||||
*/
|
||||
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
|
||||
{
|
||||
;// ESP32-S2 do not support
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get I2C interrupt status register address
|
||||
*/
|
||||
static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
|
||||
{
|
||||
return &dev->int_status;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
|
||||
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
|
||||
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Get the I2C hardware instance
|
||||
#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == 0) ? &I2C0 : &I2C1)
|
||||
// Get the I2C hardware FIFO address
|
||||
#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num))
|
||||
// I2C master TX interrupt bitmap
|
||||
#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
|
||||
// I2C master RX interrupt bitmap
|
||||
#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
|
||||
// I2C slave TX interrupt bitmap
|
||||
#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M)
|
||||
// I2C slave RX interrupt bitmap
|
||||
#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
|
||||
// I2C max timeout value
|
||||
#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V
|
||||
|
||||
#define I2C_LL_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */
|
||||
|
||||
/**
|
||||
* @brief I2C interrupt event
|
||||
*/
|
||||
typedef enum {
|
||||
I2C_INTR_EVENT_ERR,
|
||||
I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */
|
||||
I2C_INTR_EVENT_NACK, /*!< I2C NACK event */
|
||||
I2C_INTR_EVENT_TOUT, /*!< I2C time out event */
|
||||
I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */
|
||||
I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */
|
||||
I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */
|
||||
I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */
|
||||
} i2c_intr_event_t;
|
||||
|
||||
/**
|
||||
* @brief Configure I2C SCL timing
|
||||
*
|
||||
@@ -931,6 +781,157 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
|
||||
*low_period = hw->scl_low_period.period;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get I2C master interrupt event
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param event Pointer to accept the interrupt event
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
|
||||
{
|
||||
typeof(hw->int_status) int_sts = hw->int_status;
|
||||
if (int_sts.arbitration_lost) {
|
||||
*event = I2C_INTR_EVENT_ARBIT_LOST;
|
||||
} else if (int_sts.nack) {
|
||||
*event = I2C_INTR_EVENT_NACK;
|
||||
} else if (int_sts.time_out) {
|
||||
*event = I2C_INTR_EVENT_TOUT;
|
||||
} else if (int_sts.end_detect) {
|
||||
*event = I2C_INTR_EVENT_END_DET;
|
||||
} else if (int_sts.trans_complete) {
|
||||
*event = I2C_INTR_EVENT_TRANS_DONE;
|
||||
} else {
|
||||
*event = I2C_INTR_EVENT_ERR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get I2C slave interrupt event
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param event Pointer to accept the interrupt event
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
|
||||
{
|
||||
typeof(hw->int_status) int_sts = hw->int_status;
|
||||
if (int_sts.tx_fifo_wm) {
|
||||
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
|
||||
} else if (int_sts.trans_complete) {
|
||||
*event = I2C_INTR_EVENT_TRANS_DONE;
|
||||
} else if (int_sts.rx_fifo_wm) {
|
||||
*event = I2C_INTR_EVENT_RXFIFO_FULL;
|
||||
} else {
|
||||
*event = I2C_INTR_EVENT_ERR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable I2C master TX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_clr.val = UINT32_MAX;
|
||||
hw->int_ena.val = I2C_LL_MASTER_TX_INT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable I2C master RX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_clr.val = UINT32_MAX;
|
||||
hw->int_ena.val = I2C_LL_MASTER_RX_INT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C master TX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C master RX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable I2C slave TX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_ena.val |= I2C_LL_SLAVE_TX_INT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable I2C slave RX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_ena.val |= I2C_LL_SLAVE_RX_INT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C slave TX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C slave RX interrupt
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
|
||||
{
|
||||
hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user