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feat: add esp32p4 APM HAL/LL API
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -14,6 +14,93 @@ extern "C" {
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#if SOC_APM_SUPPORTED
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#include "hal/apm_ll.h"
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#if CONFIG_IDF_TARGET_ESP32P4
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/**
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* @brief DMA configurable region configuration data.
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*/
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typedef struct {
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apm_ll_dma_master_t dma_master; /* DMA master whose access permission to be configured.*/
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uint32_t pms_r_mask; /* Read permission mask. */
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uint32_t pms_w_mask; /* Write permission mask. */
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} apm_hal_dma_region_config_data_t;
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/**
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* @brief Configure HP peripherals access permission for the HP CPU0/1.
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*
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* @param master_id HP CPU0/1
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* @param hp_peri HP peripheral whose access permission to be configured.
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* @param enable Permission enable/disable
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*/
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void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri,
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apm_ll_secure_mode_t sec_mode, bool enable);
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/**
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* @brief Configure LP peripherals access permission for the LP CPU.
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*
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* @param lp_peri LP peripheral whose access permission to be configured.
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* @param enable Permission enable/disable
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*/
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void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable);
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/**
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* @brief Configure peripherals configurable address ranges.
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*
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* @param regn_num Configurable address range number.
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* @param regn_low_addr Configurable address range start address.
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* @param regn_high_addr Configurable address range end address.
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*/
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void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr,
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uint32_t regn_high_addr);
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/**
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* @brief Configure peripherals configurable address ranges.
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*
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* @param master_id LP CPU and HP CPU0/1
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* @param sec_mode CPU privilege mode (Machine/User) which corresponds to (TEE/REE).
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* @param regn_num Configurable address range number.
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* @param regn_pms Configurable address range permission setting(2-bits field).
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* Bit 0: Region 0 permission enable/disable.
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* Bit 1: Region 1 permission enable/disable.
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* @return Configuration performed successfully?
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*/
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int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode,
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uint32_t regn_num, uint32_t regn_pms);
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/**
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* @brief Configure APM controller clock gating.
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*
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* @param apm_ctrl APM controller (LP_PERI/HP_PERI/HP_DMA/LP2HP_PERI/HP2LP_PERI).
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* @param enable Permission enable/disable.
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* enable: Enable automatic clock gating.
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* disable: Keep the clock always on.
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* @return Clock gating set successfully?
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*/
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int apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable);
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/**
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* @brief Configure DMA configurable address range low address.
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*
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* @param regn_num Configurable DMA address range number.
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* @param regn_low_addr Configurable DMA address range start address.
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* @param regn_high_addr Configurable DMA address range end address.
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*/
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void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr);
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/**
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* @brief Configure DMA configurable address range read permission.
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*
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* @param pms_data DMA configurable region configuration data.
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* @param dma_master DMA master whose access permission to be configured.
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* @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission.
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* 0: Disable read permission.
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* 1: Enable read permission.
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*/
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void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data);
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#else
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/**
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* @brief Region configuration data.
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*/
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@@ -157,7 +244,9 @@ void apm_hal_apm_ctrl_reset_event_enable(bool enable);
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*/
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esp_err_t apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path);
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#endif
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#endif //CONFIG_IDF_TARGET_ESP32P4
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#endif //SOC_APM_SUPPORTED
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#ifdef __cplusplus
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}
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