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rmt: support pll clock source on esp32c6
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@@ -9,6 +9,7 @@ from pytest_embedded import Dut
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@pytest.mark.esp32s2
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@pytest.mark.esp32s3
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@pytest.mark.esp32c3
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@pytest.mark.esp32c6
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@pytest.mark.generic
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@pytest.mark.parametrize(
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'config',
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