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rmt: support pll clock source on esp32c6

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This commit is contained in:
morris
2022-12-14 19:00:58 +08:00
parent c6e452a871
commit 32cd193ddf
11 changed files with 42 additions and 24 deletions
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12
components/hal/esp32c6/include/hal/rmt_ll.h
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@@ -95,9 +95,12 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
PCR.rmt_sclk_conf.rmt_sclk_div_a = divider_numerator;
PCR.rmt_sclk_conf.rmt_sclk_div_b = divider_denominator;
switch (src) {
case RMT_CLK_SRC_APB:
case RMT_CLK_SRC_PLL_F80M:
PCR.rmt_sclk_conf.rmt_sclk_sel = 1;
break;
case RMT_CLK_SRC_RC_FAST:
PCR.rmt_sclk_conf.rmt_sclk_sel = 2;
break;
case RMT_CLK_SRC_XTAL:
PCR.rmt_sclk_conf.rmt_sclk_sel = 3;
break;
@@ -758,10 +761,13 @@ static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
{
rmt_clock_source_t clk_src = RMT_CLK_SRC_APB;
rmt_clock_source_t clk_src = RMT_CLK_SRC_PLL_F80M;
switch (PCR.rmt_sclk_conf.rmt_sclk_sel) {
case 1:
clk_src = RMT_CLK_SRC_APB;
clk_src = RMT_CLK_SRC_PLL_F80M;
break;
case 2:
clk_src = RMT_CLK_SRC_RC_FAST;
break;
case 3:
clk_src = RMT_CLK_SRC_XTAL;