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https://github.com/espressif/esp-idf.git
synced 2025-09-02 06:38:47 +00:00
fix(hal): check the public header files and fix violations
fix(hal/include): fix header violations in hal component fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Add comment for a far away `#endif` fix(hal/include): change scope for cpp guard ci: Remove components/hal/ comment from public headers check exceptions Add missing include macro sdkconfig.h for header files Add missing include macro stdbool.h for header files Add missing include macro stdint.h for header files Add missing capability guard macro for header files Add missing cpp guard macro for header files Remove some useless include macros Add some missing `inline` attribute for functions defined in header files Remove components/hal/ from public headers check exceptions fix(hal/include): fix invalid licenses fix(hal/include): fix invalid licenses fix(hal/include): add missing soc_caps.h fix(hal): include soc_caps.h before cap macro is used fix(hal): Remove unnecessary target check fix(hal): fix header and macro problems Add missing include macro Remove loop dependency in hal Add comment for far-away endif fix(hal): Add missing soc_caps.h ci: update check_copyright_ignore.txt Change the sequence of `#include` macro, cpp guard macro Change the wrap scope of capacity macro fix(hal): Change position of C++ guard to pass test
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@@ -6,10 +6,12 @@
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#pragma once
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#include <stdbool.h>
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#include "soc/ext_mem_defs.h"
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#include "soc/memprot_defs.h"
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#include "hal/memprot_types.h"
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#include "soc/sensitive_reg.h"
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#include "soc/periph_defs.h"
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/* Uncomment to enable MPS debug assertions on false register writes.
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* It irregularly happens the PMS registers cannot be written which causes unpredictable malfunction of the Memprot feature
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@@ -27,15 +29,14 @@ extern "C" {
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//highest address of each Level slot in the SRAM's 3rd memory region (I/D access, 416kB)
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//quick resolver of split-address category bits
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static const intptr_t sram_rg3_level_hlimits[] = {
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0x4037FFFF, //level 2 (32KB)
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0x4038FFFF, //level 3 (64KB)
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0x4039FFFF, //level 4 (64KB)
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0x403AFFFF, //level 5 (64KB)
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0x403BFFFF, //level 6 (64KB)
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0x403CFFFF, //level 7 (64KB)
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0x403DFFFF //level 8 (64KB)
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};
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// 0x4037FFFF level 2 (32KB)
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// 0x4038FFFF level 3 (64KB)
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// 0x4039FFFF level 4 (64KB)
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// 0x403AFFFF level 5 (64KB)
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// 0x403BFFFF level 6 (64KB)
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// 0x403CFFFF level 7 (64KB)
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// 0x403DFFFF level 8 (64KB)
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#define SRAM_RG3_LEVEL_HLIMITS(level) ((intptr_t[]) {0x4037FFFF,0x4038FFFF,0x4039FFFF,0x403AFFFF,0x403BFFFF,0x403CFFFF,0x403DFFFF} [(level)])
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/* ******************************************************************************************************
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* *** COMMON ***
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@@ -178,7 +179,7 @@ static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t add
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//set category bits for given split line
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uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA};
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for (size_t x=0; x<7; x++) {
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if (addr <= sram_rg3_level_hlimits[x]) {
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if (addr <= SRAM_RG3_LEVEL_HLIMITS(x)) {
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cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA;
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break;
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} else {
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@@ -1252,7 +1253,7 @@ static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t add
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//set category bits for given split line
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uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA};
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for (size_t x=0; x<7; x++) {
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if (addr <= MAP_IRAM_TO_DRAM(sram_rg3_level_hlimits[x])) {
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if (addr <= MAP_IRAM_TO_DRAM(SRAM_RG3_LEVEL_HLIMITS(x))) {
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cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA;
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break;
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} else {
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