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fix(sdmmc): move DMA descriptor refilling into the ISR

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Previously, as DMA descriptors were processed, the task performing
SDMMC transfer would get woken up and would refill the descriptors.
This design didn't work correctly when higher priority tasks occupied
the CPU for too long, resulting in SDMMC transfer timing out.

This change moves DMA descriptor refilling into SDMMC ISR. Now the
"DMA done" interrupt is delivered back to task context only when
the entire transfer is completed.

Closes https://github.com/espressif/esp-idf/issues/13934
This commit is contained in:
Ivan Grokhotkov
2025-02-21 16:04:01 +01:00
committed by Armando (Dou Yiwen)
parent e4cf819104
commit 335027b731
6 changed files with 123 additions and 105 deletions
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8
components/hal/esp32/include/hal/sdmmc_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -74,6 +74,12 @@ extern "C" {
SDMMC_LL_EVENT_SBE | SDMMC_LL_EVENT_ACD |\
SDMMC_LL_EVENT_EBE)
// DMA interrupts (idsts register)
#define SDMMC_LL_EVENT_DMA_TI SDMMC_IDMAC_INTMASK_TI
#define SDMMC_LL_EVENT_DMA_RI SDMMC_IDMAC_INTMASK_RI
#define SDMMC_LL_EVENT_DMA_NI SDMMC_IDMAC_INTMASK_NI
#define SDMMC_LL_EVENT_DMA_MASK 0x1f //NI and AI will be indicated by TI/RI and FBE/DU respectively
/**
* SDMMC capabilities
*/

8
components/hal/esp32p4/include/hal/sdmmc_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -77,6 +77,12 @@ extern "C" {
SDMMC_LL_EVENT_SBE | SDMMC_LL_EVENT_ACD |\
SDMMC_LL_EVENT_EBE)
// DMA interrupts (idsts register)
#define SDMMC_LL_EVENT_DMA_TI SDMMC_IDMAC_INTMASK_TI
#define SDMMC_LL_EVENT_DMA_RI SDMMC_IDMAC_INTMASK_RI
#define SDMMC_LL_EVENT_DMA_NI SDMMC_IDMAC_INTMASK_NI
#define SDMMC_LL_EVENT_DMA_MASK 0x1f //NI and AI will be indicated by TI/RI and FBE/DU respectively
/**
* SDMMC capabilities
*/

8
components/hal/esp32s3/include/hal/sdmmc_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -74,6 +74,12 @@ extern "C" {
SDMMC_LL_EVENT_SBE | SDMMC_LL_EVENT_ACD |\
SDMMC_LL_EVENT_EBE)
// DMA interrupts (idsts register)
#define SDMMC_LL_EVENT_DMA_TI SDMMC_IDMAC_INTMASK_TI
#define SDMMC_LL_EVENT_DMA_RI SDMMC_IDMAC_INTMASK_RI
#define SDMMC_LL_EVENT_DMA_NI SDMMC_IDMAC_INTMASK_NI
#define SDMMC_LL_EVENT_DMA_MASK 0x1f //NI and AI will be indicated by TI/RI and FBE/DU respectively
/**
* SDMMC capabilities
*/