alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-30 19:19:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(clk): Add basic clock support for esp32c61

Browse Source 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
This commit is contained in:
Song Ruo Jing
2024-07-19 17:10:06 +08:00
parent d92c09a0ad
commit 335d39b869
53 changed files with 1193 additions and 741 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/hal/esp32h2/include/hal/clk_tree_ll.h
View File

@@ -43,7 +43,7 @@ Set the frequency division factor of ref_tick
The FOSC of rtc calibration uses the 32 frequency division clock for ECO2,
So the frequency division factor of ref_tick must be greater than or equal to 32
*/
#define CLK_LL_RC_FAST_TICK_DIV_BITS 5
#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5
#define REG_FOSC_TICK_NUM 255
/**
@@ -656,7 +656,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin
/**
* @brief Get RC_FAST_CLK divider
*
* @return Divider. Divider = (CK8M_DIV_SEL + 1).
* @return Divider
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
{