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feat(ledc): support ledc on esp32c5

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igor.udot
2024-05-15 16:35:06 +08:00
parent b1a5d80bcc
commit 33fa42ca74
13 changed files with 2816 additions and 42 deletions
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4
components/esp_driver_ledc/src/ledc.c
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@@ -571,8 +571,10 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk);
/* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */
#if SOC_LIGHT_SLEEP_SUPPORTED
extern void esp_sleep_periph_use_8m(bool use_or_not);
esp_sleep_periph_use_8m(glb_clk == LEDC_SLOW_CLK_RC_FAST);
#endif
}
/* The divisor is correct, we can write in the hardware. */
@@ -672,7 +674,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
if (!new_speed_mode_ctx_created && !p_ledc_obj[speed_mode]) {
return ESP_ERR_NO_MEM;
}
#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4)
#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5)
// On such targets, the default ledc core(global) clock does not connect to any clock source
// Set channel configurations and update bits before core clock is on could lead to error
// Therefore, we should connect the core clock to a real clock source to make it on before any ledc register operation