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refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC
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20
components/soc/esp32c6/esp_cpu_intr.c
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20
components/soc/esp32c6/esp_cpu_intr.c
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_cpu.h"
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#include "esp_riscv_intr.h"
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void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
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{
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/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
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* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
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*
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* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
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/* TODO: IDF-8655, we may need to reserve more interrupts once we have Wifi and BT */
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intr_desc_ret->priority = 1;
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intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
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intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
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}
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