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Merge branch 'refactor/adc_unify_adc_unit' into 'master'

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adc: adc single driver NG pre-step - unify adc_ll_num_t and adc_unit_t

See merge request espressif/esp-idf!17408
This commit is contained in:
Armando (Dou Yiwen)
2022-03-18 20:29:36 +08:00
parent 93987e6b79 109f2a7449
commit 36457b1346
40 changed files with 830 additions and 918 deletions
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8
components/hal/esp32/adc_hal.c
View File

@@ -20,11 +20,11 @@ int adc_hal_hall_convert(void)
int hall_value;
// convert for 4 times with different phase and outputs
adc_ll_hall_phase_disable(); // hall phase
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp0 );
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn0 );
adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_0, &Sens_Vp0 );
adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_3, &Sens_Vn0 );
adc_ll_hall_phase_enable();
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp1 );
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn1 );
adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_0, &Sens_Vp1 );
adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_3, &Sens_Vn1 );
hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
return hall_value;
}

49
components/hal/esp32/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (1)
#define SOC_ADC2_DATA_INVERT_DEFAULT (1)
/*---------------------------------------------------------------
Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
/*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (16)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (16)
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_HAL_PWDET_CCT_DEFAULT (4)

103
components/hal/esp32/include/hal/adc_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,11 +19,6 @@
extern "C" {
#endif
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
@@ -182,11 +177,11 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
*
* @prarm adc_n ADC unit.
*/
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SYSCON.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SYSCON.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
}
}
@@ -210,11 +205,11 @@ static inline void adc_ll_digi_set_data_source(bool src)
* @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 16.
*/
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len)
static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1;
}
}
@@ -229,7 +224,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 15.
* @param pattern Stored conversion rules, see ``adc_digi_pattern_table_t``.
*/
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{
uint32_t tab;
uint8_t index = pattern_index / 4;
@@ -255,12 +250,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
}
pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
if (table.unit == ADC_NUM_1) {
if (table.unit == ADC_UNIT_1) {
tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
@@ -273,12 +268,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n)
static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SYSCON.saradc_ctrl.sar1_patt_p_clear = 1;
SYSCON.saradc_ctrl.sar1_patt_p_clear = 0;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SYSCON.saradc_ctrl.sar2_patt_p_clear = 1;
SYSCON.saradc_ctrl.sar2_patt_p_clear = 0;
}
@@ -328,11 +323,11 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
*
* @param div Division factor.
*/
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
}
}
@@ -343,12 +338,12 @@ static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
* @param adc_n ADC unit.
* @param bits Output data bits width option, see ``adc_bits_width_t``.
*/
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits)
static inline void adc_ll_rtc_set_output_format(adc_unit_t adc_n, adc_bits_width_t bits)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_start_force.sar1_bit_width = bits;
SENS.sar_read_ctrl.sar1_sample_bit = bits;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_start_force.sar2_bit_width = bits;
SENS.sar_read_ctrl2.sar2_sample_bit = bits;
}
@@ -362,11 +357,11 @@ static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_wid
* @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn.
*/
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
static inline void adc_ll_rtc_enable_channel(adc_unit_t adc_n, int channel)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_meas_start1.sar1_en_pad = (1 << channel); //only one channel is selected.
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected.
}
}
@@ -378,11 +373,11 @@ static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
static inline void adc_ll_rtc_disable_channel(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_meas_start1.sar1_en_pad = 0; //only one channel is selected.
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_meas_start2.sar2_en_pad = 0; //only one channel is selected.
}
}
@@ -395,13 +390,13 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
* @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn.
*/
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
static inline void adc_ll_rtc_start_convert(adc_unit_t adc_n, int channel)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
SENS.sar_meas_start1.meas1_start_sar = 0;
SENS.sar_meas_start1.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0
SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1
}
@@ -415,12 +410,12 @@ static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
* -true : The conversion process is finish.
* -false : The conversion process is not finish.
*/
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
static inline bool adc_ll_rtc_convert_is_done(adc_unit_t adc_n)
{
bool ret = true;
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
ret = (bool)SENS.sar_meas_start1.meas1_done_sar;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
ret = (bool)SENS.sar_meas_start2.meas2_done_sar;
}
return ret;
@@ -433,12 +428,12 @@ static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
* @return
* - Converted value.
*/
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
static inline int adc_ll_rtc_get_convert_value(adc_unit_t adc_n)
{
int ret_val = 0;
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar);
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar);
}
return ret_val;
@@ -449,11 +444,11 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_rtc_output_invert(adc_unit_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_read_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_read_ctrl2.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
}
}
@@ -466,7 +461,7 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
* @return
* - 0: The data is correct to use.
*/
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data)
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_unit_t adc_n, uint16_t raw_data)
{
/* ADC1 don't need check data */
return ADC_RTC_DATA_OK;
@@ -475,11 +470,11 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
/**
* Set the attenuation of a particular channel on ADCn.
*/
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
static inline void adc_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
}
}
@@ -491,9 +486,9 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
* @param channel ADCn channel number.
* @return atten The attenuation option.
*/
static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel)
static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
} else {
return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
@@ -531,9 +526,9 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
* @param adc_n ADC unit.
* @param ctrl ADC controller.
*/
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
switch ( ctrl ) {
case ADC_LL_CTRL_RTC:
SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
@@ -559,7 +554,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t
default:
break;
}
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
switch ( ctrl ) {
case ADC_LL_CTRL_RTC:
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
@@ -669,9 +664,11 @@ static inline void adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl
* @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output
*/
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{
if (adc != ADC_NUM_2) return;
if (adc != ADC_UNIT_2) {
return;
}
if (en) {
RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode