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Merge branch 'refactor/adc_unify_adc_unit' into 'master'

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adc: adc single driver NG pre-step - unify adc_ll_num_t and adc_unit_t

See merge request espressif/esp-idf!17408
This commit is contained in:
Armando (Dou Yiwen)
2022-03-18 20:29:36 +08:00
parent 93987e6b79 109f2a7449
commit 36457b1346
40 changed files with 830 additions and 918 deletions
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49
components/hal/esp32s2/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (0)
#define SOC_ADC2_DATA_INVERT_DEFAULT (0)
/*---------------------------------------------------------------
Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
/*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (5)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (3)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (2)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (3)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (2)
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_HAL_PWDET_CCT_DEFAULT (4)

174
components/hal/esp32s2/include/hal/adc_ll.h
View File

@@ -27,12 +27,6 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */
@@ -211,11 +205,11 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 16.
*/
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len)
static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_len = patt_len - 1;
}
}
@@ -230,7 +224,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 15.
* @param pattern Stored conversion rules.
*/
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{
uint32_t tab;
uint8_t index = pattern_index / 4;
@@ -238,12 +232,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
adc_ll_digi_pattern_table_t pattern = {0};
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 4);
if (table.unit == ADC_NUM_1) {
if (table.unit == ADC_UNIT_1) {
tab = APB_SARADC.sar1_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
APB_SARADC.sar1_patt_tab[index] = tab; // Write back
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
tab = APB_SARADC.sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
@@ -256,12 +250,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n)
static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_p_clear = 1;
APB_SARADC.ctrl.sar1_patt_p_clear = 0;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_p_clear = 1;
APB_SARADC.ctrl.sar2_patt_p_clear = 0;
}
@@ -284,11 +278,11 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
* @param adc_n ADC unit.
* @param inv_en data invert or not.
*/
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
}
}
@@ -367,12 +361,12 @@ static inline void adc_ll_digi_controller_clk_disable(void)
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n)
static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.filter_ctrl.adc1_filter_reset = 1;
APB_SARADC.filter_ctrl.adc1_filter_reset = 0;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.filter_ctrl.adc2_filter_reset = 1;
APB_SARADC.filter_ctrl.adc2_filter_reset = 0;
}
@@ -384,7 +378,7 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n)
* @param adc_n ADC unit.
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
*/
static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor)
static inline void adc_ll_digi_filter_set_factor(adc_unit_t adc_n, adc_digi_filter_mode_t factor)
{
int mode = 0;
switch (factor) {
@@ -395,9 +389,9 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi
case ADC_DIGI_FILTER_IIR_64: mode = 64; break;
default: mode = 8; break;
}
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.filter_ctrl.adc1_filter_factor = mode;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.filter_ctrl.adc2_filter_factor = mode;
}
}
@@ -408,12 +402,12 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi
* @param adc_n ADC unit.
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
*/
static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor)
static inline void adc_ll_digi_filter_get_factor(adc_unit_t adc_n, adc_digi_filter_mode_t *factor)
{
int mode = 0;
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
mode = APB_SARADC.filter_ctrl.adc1_filter_factor;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
mode = APB_SARADC.filter_ctrl.adc2_filter_factor;
}
switch (mode) {
@@ -433,11 +427,11 @@ static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_fi
* @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit.
*/
static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
static inline void adc_ll_digi_filter_enable(adc_unit_t adc_n, bool enable)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.filter_ctrl.adc1_filter_en = enable;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.filter_ctrl.adc2_filter_en = enable;
}
}
@@ -450,11 +444,11 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
* @param adc_n ADC unit.
* @return Filtered data.
*/
static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
static inline uint32_t adc_ll_digi_filter_read_data(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc1_filter_data);
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc2_filter_data);
}
}
@@ -467,11 +461,11 @@ static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
* @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt.
* false: If ADC_OUT < threshold, Generates monitor interrupt.
*/
static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger)
static inline void adc_ll_digi_monitor_set_mode(adc_unit_t adc_n, bool is_larger)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.thres_ctrl.adc1_thres_mode = is_larger;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.thres_ctrl.adc2_thres_mode = is_larger;
}
}
@@ -483,11 +477,11 @@ static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larg
* @param adc_n ADC unit.
* @param threshold Monitor threshold.
*/
static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t threshold)
static inline void adc_ll_digi_monitor_set_thres(adc_unit_t adc_n, uint32_t threshold)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.thres_ctrl.adc1_thres = threshold;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.thres_ctrl.adc2_thres = threshold;
}
}
@@ -498,11 +492,11 @@ static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t th
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit.
*/
static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable)
static inline void adc_ll_digi_monitor_enable(adc_unit_t adc_n, bool enable)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
APB_SARADC.thres_ctrl.adc1_thres_en = enable;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
APB_SARADC.thres_ctrl.adc2_thres_en = enable;
}
}
@@ -578,11 +572,11 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
*
* @param div Division factor.
*/
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
}
}
@@ -594,7 +588,7 @@ static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
* @prarm adc_n ADC unit.
* @prarm bits Output data bits width option.
*/
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits)
static inline void adc_ll_rtc_set_output_format(adc_unit_t adc_n, adc_bits_width_t bits)
{
return;
}
@@ -607,11 +601,11 @@ static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_wid
* @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn.
*/
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
static inline void adc_ll_rtc_enable_channel(adc_unit_t adc_n, int channel)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected.
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected.
}
}
@@ -624,11 +618,11 @@ static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
* @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn.
*/
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
static inline void adc_ll_rtc_disable_channel(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected.
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected.
}
}
@@ -641,13 +635,13 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
* @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn.
*/
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
static inline void adc_ll_rtc_start_convert(adc_unit_t adc_n, int channel)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0
SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1
}
@@ -661,12 +655,12 @@ static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
* -true : The conversion process is finish.
* -false : The conversion process is not finish.
*/
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
static inline bool adc_ll_rtc_convert_is_done(adc_unit_t adc_n)
{
bool ret = true;
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar;
}
return ret;
@@ -679,12 +673,12 @@ static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
* @return
* - Converted value.
*/
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
static inline int adc_ll_rtc_get_convert_value(adc_unit_t adc_n)
{
int ret_val = 0;
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar);
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar);
}
return ret_val;
@@ -696,11 +690,11 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
* @param adc_n ADC unit.
* @param inv_en data invert or not.
*/
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_rtc_output_invert(adc_unit_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
}
}
@@ -710,12 +704,12 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
static inline void adc_ll_rtc_intr_enable(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 1;
RTCCNTL.int_ena.rtc_saradc1 = 1;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_int_en = 1;
RTCCNTL.int_ena.rtc_saradc2 = 1;
}
@@ -726,12 +720,12 @@ static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n)
static inline void adc_ll_rtc_intr_disable(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 0;
RTCCNTL.int_ena.rtc_saradc1 = 0;
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_int_en = 0;
RTCCNTL.int_ena.rtc_saradc2 = 0;
}
@@ -769,10 +763,10 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
* - 2: The data is invalid. The current controller process was interrupted by a higher priority controller.
* - -1: The data is error.
*/
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data)
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_unit_t adc_n, uint16_t raw_data)
{
/* ADC1 don't need check data */
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
return ADC_RTC_DATA_OK;
}
adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data;
@@ -820,11 +814,11 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
* @param channel ADCn channel number.
* @param atten The attenuation option.
*/
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
static inline void adc_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
}
}
@@ -836,9 +830,9 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
* @param channel ADCn channel number.
* @return atten The attenuation option.
*/
static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel)
static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
} else {
return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
@@ -879,9 +873,9 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
* @param adc_n ADC unit.
* @param ctrl ADC controller.
*/
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
@@ -901,7 +895,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t
default:
break;
}
} else { // adc_n == ADC_NUM_2
} else { // adc_n == ADC_UNIT_2
switch (ctrl) {
//If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2.
case ADC_LL_CTRL_ARB:
@@ -1018,9 +1012,9 @@ static inline void adc_ll_disable_sleep_controller(void)
/**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/
static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
@@ -1037,7 +1031,7 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage.
*/
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd)
{
/* Should be called before writing I2C registers. */
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
@@ -1046,7 +1040,7 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
/* Enable/disable internal connect GND (for calibration). */
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else {
@@ -1066,9 +1060,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
*
* @param adc_n ADC index number.
*/
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
@@ -1082,7 +1076,7 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
*
* @param adc_n ADC index number.
*/
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param)
static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{
uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF;
@@ -1091,7 +1085,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
if (adc_n == ADC_NUM_1) {
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else {
@@ -1112,7 +1106,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
* @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output
*/
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{
/* Should be called before writing I2C registers. */
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
@@ -1120,7 +1114,7 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
if (en) {
if (adc == ADC_NUM_1) {
if (adc == ADC_UNIT_1) {
/* Config test mux to route v_ref to ADC1 Channels */
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);