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hal: always inline clk_tree_ll functions

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This commit is contained in:
Alexey Lapshin
2023-02-13 12:36:51 +07:00
parent 84ff4d6e37
commit 36d0e275a0
8 changed files with 226 additions and 226 deletions
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66
components/hal/esp32/include/hal/clk_tree_ll.h
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@@ -127,7 +127,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
/**
* @brief Power up APLL circuit
*/
static inline void clk_ll_apll_enable(void)
static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
@@ -136,7 +136,7 @@ static inline void clk_ll_apll_enable(void)
/**
* @brief Power down APLL circuit
*/
static inline void clk_ll_apll_disable(void)
static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
@@ -147,7 +147,7 @@ static inline void clk_ll_apll_disable(void)
*
* @return True if APLL is under force power down; otherwise false
*/
static inline bool clk_ll_apll_is_fpd(void)
static inline __attribute__((always_inline)) bool clk_ll_apll_is_fpd(void)
{
return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
}
@@ -160,7 +160,7 @@ static inline bool clk_ll_apll_is_fpd(void)
* @param[out] sdm1 Frequency adjustment parameter, 0..255
* @param[out] sdm2 Frequency adjustment parameter, 0..63
*/
static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
{
*o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV);
*sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0);
@@ -177,7 +177,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3
* @param sdm1 Frequency adjustment parameter, 0..255
* @param sdm2 Frequency adjustment parameter, 0..63
*/
static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
static inline __attribute__((always_inline)) void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
{
uint8_t sdm_stop_val_2 = CLK_LL_APLL_SDM_STOP_VAL_2_REV1;
if (is_rev0) {
@@ -196,7 +196,7 @@ static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t
/**
* @brief Set APLL calibration parameters
*/
static inline void clk_ll_apll_set_calibration(void)
static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void)
{
REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1);
REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2);
@@ -208,7 +208,7 @@ static inline void clk_ll_apll_set_calibration(void)
*
* @return True if calibration is done; otherwise false
*/
static inline bool clk_ll_apll_calibration_is_done(void)
static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void)
{
return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END);
}
@@ -218,7 +218,7 @@ static inline bool clk_ll_apll_calibration_is_done(void)
*
* @param mode Used to determine the xtal32k configuration parameters
*/
static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
{
// Configure xtal32k
// Default mode as CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL
@@ -244,7 +244,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
/**
* @brief Disable the 32kHz crystal oscillator
*/
static inline void clk_ll_xtal32k_disable(void)
static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
{
// Disable xtal32k xpd status
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
@@ -255,7 +255,7 @@ static inline void clk_ll_xtal32k_disable(void)
*
* @return True if the 32kHz XTAL is enabled
*/
static inline bool clk_ll_xtal32k_is_enabled(void)
static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
{
return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
}
@@ -283,7 +283,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
*
* @return True if the oscillator is enabled
*/
static inline bool clk_ll_rc_fast_is_enabled(void)
static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
}
@@ -296,7 +296,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
* so is not exposed in the code.
* The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
*/
static inline void clk_ll_rc_fast_d256_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
}
@@ -307,7 +307,7 @@ static inline void clk_ll_rc_fast_d256_enable(void)
*
* Disabling this divider could reduce power consumption.
*/
static inline void clk_ll_rc_fast_d256_disable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
}
@@ -317,7 +317,7 @@ static inline void clk_ll_rc_fast_d256_disable(void)
*
* @return True if the divided output is enabled
*/
static inline bool clk_ll_rc_fast_d256_is_enabled(void)
static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
}
@@ -325,7 +325,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void)
/**
* @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
*/
static inline void clk_ll_rc_fast_digi_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
@@ -333,7 +333,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
/**
* @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
*/
static inline void clk_ll_rc_fast_digi_disable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
@@ -343,7 +343,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
*
* @return True if the digital RC_FAST_CLK is enabled
*/
static inline bool clk_ll_rc_fast_digi_is_enabled(void)
static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
@@ -351,7 +351,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
/**
* @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
*/
static inline void clk_ll_rc_fast_d256_digi_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
}
@@ -359,7 +359,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void)
/**
* @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
*/
static inline void clk_ll_rc_fast_d256_digi_disable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
}
@@ -367,7 +367,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void)
/**
* @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
*/
static inline void clk_ll_xtal32k_digi_enable(void)
static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
}
@@ -375,7 +375,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
/**
* @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
*/
static inline void clk_ll_xtal32k_digi_disable(void)
static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
}
@@ -385,7 +385,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
*
* @return True if the digital XTAL32K_CLK is enabled
*/
static inline bool clk_ll_xtal32k_digi_is_enabled(void)
static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
}
@@ -395,7 +395,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void)
*
* @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
*/
static inline uint32_t clk_ll_bbpll_get_freq_mhz(void)
static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
{
// ESP32 BBPLL frequency is determined by the cpu freq sel
uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
@@ -641,7 +641,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
*
* @return Divider. Returns 0 means invalid.
*/
static inline uint32_t clk_ll_cpu_get_divider_from_apll(void)
static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void)
{
// APLL path divider choice shares the same register with CPUPERIOD_SEL
uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
@@ -695,7 +695,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
*
* @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
*/
static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
{
switch (in_sel) {
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -718,7 +718,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
*
* @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
*/
static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
{
uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
switch (clk_sel) {
@@ -739,7 +739,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
*
* @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
*/
static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
{
switch (in_sel) {
case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
@@ -759,7 +759,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
*
* @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
*/
static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
{
uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
switch (clk_sel) {
@@ -788,7 +788,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
*
* @return Divider. Divider = (CK8M_DIV_SEL + 1).
*/
static inline uint32_t clk_ll_rc_fast_get_divider(void)
static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
}
@@ -804,7 +804,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
* otherwise there will be a conflict with the low bit, which is used to disable logs
* in the ROM code.
*/
static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
{
// Read the status of whether disabling logging from ROM code
uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -857,7 +857,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3
*
* @return The stored APB frequency, in Hz
*/
static inline uint32_t clk_ll_apb_load_freq_hz(void)
static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void)
{
// Read from RTC storage register
uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12;
@@ -875,7 +875,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void)
*
* @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
*/
static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
{
REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
}
@@ -887,7 +887,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
*
* @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
*/
static inline uint32_t clk_ll_rtc_slow_load_cal(void)
static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
{
return REG_READ(RTC_SLOW_CLK_CAL_REG);
}