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Merge branch 'bugfix/rmt_p4_test' into 'master'

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fix(rmt): DMA descriptor alignment respect the cache line size

Closes IDF-8961

See merge request espressif/esp-idf!28296
This commit is contained in:
morris
2024-01-08 12:43:58 +08:00
parent daa729eae4 d97a46160d
commit 36d6ee9e61
9 changed files with 61 additions and 53 deletions
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14
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -214,11 +214,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#if SOC_CLK_TREE_SUPPORTED
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
#else
#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
#endif
/**
* @brief Type of RMT clock source
@@ -227,11 +223,7 @@ typedef enum {
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
#else
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
#endif
} soc_periph_rmt_clk_src_t;
/**
@@ -240,11 +232,7 @@ typedef enum {
typedef enum {
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
#if SOC_CLK_TREE_SUPPORTED
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
#else
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
#endif
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////