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feat(spi_flash): Adjust flash clock to real 80M clock, and support 32bit address on eco1

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This commit is contained in:
C.S.M
2024-05-27 12:03:49 +08:00
parent 8541242860
commit 374c89097f
18 changed files with 242 additions and 26 deletions
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8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -1235,6 +1235,14 @@ config SOC_MEMSPI_TIMING_TUNING_BY_DQS
bool
default y
config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y

5
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -492,7 +492,7 @@
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
//#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) //TODO: IDF-7518
// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) // Cannot pass pure RAM build
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
@@ -500,6 +500,9 @@
// #define SOC_SPI_MEM_SUPPORT_WRAP (1) // IDFCI-2073 The feature cannot be treated as supported on P4
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1