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feat(spi_flash): Adjust flash clock to real 80M clock, and support 32bit address on eco1
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@@ -54,6 +54,8 @@
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#include "bootloader_flash_config.h"
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#include "esp_compiler.h"
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#include "esp_rom_efuse.h"
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#if CONFIG_SPIRAM
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#include "esp_private/esp_psram_io.h"
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#endif
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@@ -288,3 +290,22 @@ uint8_t esp_mspi_get_io(esp_mspi_io_t io)
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return s_mspi_io_num_default[io];
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#endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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}
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#if !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM // IDF-10019
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esp_err_t IRAM_ATTR esp_mspi_32bit_address_flash_feature_check(void)
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{
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
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ESP_EARLY_LOGE(TAG, "32bit address (flash over 16MB) has high risk on this chip");
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return ESP_ERR_NOT_SUPPORTED;
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#elif CONFIG_IDF_TARGET_ESP32P4
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// IDF-10019
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unsigned chip_version = efuse_hal_chip_revision();
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if (unlikely(!ESP_CHIP_REV_ABOVE(chip_version, 1))) {
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ESP_EARLY_LOGE(TAG, "32bit address (flash over 16MB) has high risk on ESP32P4 ECO0");
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return ESP_ERR_NOT_SUPPORTED;
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}
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#endif
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return ESP_OK;
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}
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#endif // !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM
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