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change(esp_hw_support): fix wifi mac rx buffer link exception caused by pll clock

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Li Shuai
2024-12-26 12:05:49 +08:00
parent 2fce894c82
commit 377914d579
3 changed files with 32 additions and 8 deletions
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19
components/hal/esp32c5/include/hal/clk_tree_ll.h
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@@ -9,16 +9,19 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "soc/chip_revision.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32c5/rom/rtc.h"
#include "hal/misc.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
@@ -420,6 +423,22 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
}
/**
* @brief Enable or disable the soc root clock auto gating logic
*
* @param ena true to enable, false to disable
*/
static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gating_bypass(bool ena)
{
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (ena) {
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
} else {
REG_SET_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
}
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*