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component/esp32 : do more fix of dualcore bug

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1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
This commit is contained in:
Tian Hao
2017-05-10 15:45:04 +08:00
parent c518325385
commit 377a1f5ea1
7 changed files with 271 additions and 128 deletions
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37
components/esp32/include/esp_assert.h Normal file
View File

@@ -0,0 +1,37 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_ASSERT_H__
#define __ESP_ASSERT_H__
#include "assert.h"
/* Assert at compile time if possible, runtime otherwise */
#ifndef __cplusplus
/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
#define TRY_STATIC_ASSERT(CONDITION, MSG) do { \
_Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG); \
assert(#MSG && (CONDITION)); \
} while(0)
#else
/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
#define TRY_STATIC_ASSERT(CONDITION, MSG) do { \
if (__builtin_constant_p(CONDITION) && !(CONDITION)) { \
extern __attribute__((error(#MSG))) void failed_compile_time_assert(void); \
failed_compile_time_assert(); \
} \
assert(#MSG && (CONDITION)); \
} while(0)
#endif /* __cplusplus */
#endif /* __ESP_ASSERT_H__ */

60
components/esp32/include/rom/cache.h
View File

@@ -15,6 +15,8 @@
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
#include "soc/dport_access.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -64,7 +66,18 @@ void mmu_init(int cpu_no);
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
{
extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
unsigned int ret;
DPORT_STALL_OTHER_CPU_START();
ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
DPORT_STALL_OTHER_CPU_END();
return ret;
}
/**
* @brief Set Ext-SRAM-Cache mmu mapping.
@@ -93,7 +106,18 @@ unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsign
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
static inline unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
{
extern unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
unsigned int ret;
DPORT_STALL_OTHER_CPU_START();
ret = cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
DPORT_STALL_OTHER_CPU_END();
return ret;
}
/**
* @brief Initialise cache access for the cpu.
@@ -103,7 +127,13 @@ unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigne
*
* @return None
*/
void Cache_Read_Init(int cpu_no);
static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
{
extern void Cache_Read_Init_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Read_Init_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @brief Flush the cache value for the cpu.
@@ -113,7 +143,13 @@ void Cache_Read_Init(int cpu_no);
*
* @return None
*/
void Cache_Flush(int cpu_no);
static inline void IRAM_ATTR Cache_Flush(int cpu_no)
{
extern void Cache_Flush_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Flush_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @brief Disable Cache access for the cpu.
@@ -123,7 +159,13 @@ void Cache_Flush(int cpu_no);
*
* @return None
*/
void Cache_Read_Disable(int cpu_no);
static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
{
extern void Cache_Read_Disable_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Read_Disable_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @brief Enable Cache access for the cpu.
@@ -133,7 +175,13 @@ void Cache_Read_Disable(int cpu_no);
*
* @return None
*/
void Cache_Read_Enable(int cpu_no);
static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
{
extern void Cache_Read_Enable_rom(int cpu_no);
DPORT_STALL_OTHER_CPU_START();
Cache_Read_Enable_rom(cpu_no);
DPORT_STALL_OTHER_CPU_END();
}
/**
* @}