mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-09 20:41:14 +00:00
component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
This commit is contained in:
Tian Hao
@@ -22,30 +22,29 @@ void esp_dport_access_stall_other_cpu_start(void);
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void esp_dport_access_stall_other_cpu_end(void);
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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#define DPORT_STAL_OTHER_CPU_START()
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#define DPORT_STAL_OTHER_CPU_END()
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#define DPORT_STALL_OTHER_CPU_START()
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#define DPORT_STALL_OTHER_CPU_END()
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#else
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#define DPORT_STAL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STAL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#define DPORT_STALL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STALL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#endif
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DPORT_DATE_REG)
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//Registers Operation {{
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#define _REG_READ(_r) (*(volatile uint32_t *)(_r))
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#define _REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//Origin access operation for the base and some special scene
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#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
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#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//write value to register
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#define DPORT_REG_WRITE(_r, _v) _REG_WRITE(_r, _v)
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE(_r, _v)
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//read value from register
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inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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{
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uint32_t val;
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DPORT_STAL_OTHER_CPU_START();
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val = _REG_READ(reg);
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DPORT_STAL_OTHER_CPU_END();
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DPORT_STALL_OTHER_CPU_START();
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val = _DPORT_REG_READ(reg);
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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@@ -54,19 +53,19 @@ inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
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//set bit or set bits to register
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#define DPORT_REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
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#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
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//clear bit or clear bits of register
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#define DPORT_REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
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#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
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//set bits of register controlled by mask
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#define DPORT_REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (DPORT_REG_READ(_r) & ~(_m)) | ((_b) & (_m)))
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#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
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//get field from register, uses field _S & _V to determine mask
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#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
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//set field to register, used when _f is not left shifted by _f##_S
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#define DPORT_REG_SET_FIELD(_r, _f, _v) (DPORT_REG_WRITE((_r),((DPORT_REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
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#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f) << (_f##_S))))|(((_v) & (_f))<<(_f##_S))))
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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@@ -90,13 +89,13 @@ inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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//read value from register
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inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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{
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uint32_t val;
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DPORT_STAL_OTHER_CPU_START();
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DPORT_STALL_OTHER_CPU_START();
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val = _READ_PERI_REG(addr);
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DPORT_STAL_OTHER_CPU_END();
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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@@ -17,6 +17,7 @@
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include "esp_assert.h"
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#endif
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//Register Bits{{
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@@ -57,98 +58,6 @@
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#define PRO_CPU_NUM (0)
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#define APP_CPU_NUM (1)
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define BIT(nr) (1UL << (nr))
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#else
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#define BIT(nr) (1 << (nr))
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#endif
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#ifndef __ASSEMBLER__
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//write value to register
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#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//read value from register
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#define REG_READ(_r) (*(volatile uint32_t *)(_r))
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
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//write value to register
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#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
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//}}
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#endif /* !__ASSEMBLER__ */
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM ( 26*1000000 )
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ APB_CLK_FREQ
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#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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//}}
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/* Overall memory map */
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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@@ -160,6 +69,7 @@
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define DR_REG_DPORT_BASE 0x3ff00000
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#define DR_REG_DPORT_END 0x3ff00FFC
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#define DR_REG_RSA_BASE 0x3ff02000
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#define DR_REG_SHA_BASE 0x3ff03000
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#define DR_REG_UART_BASE 0x3ff40000
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@@ -210,6 +120,155 @@
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#define DR_REG_PWM3_BASE 0x3ff70000
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#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define BIT(nr) (1UL << (nr))
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#else
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#define BIT(nr) (1 << (nr))
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#endif
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#ifndef __ASSEMBLER__
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
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#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
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#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
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#else
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#define ASSERT_IF_DPORT_REG(_r, OP)
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#endif
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//write value to register
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#define REG_WRITE(_r, _v) ({ \
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ASSERT_IF_DPORT_REG(_r, REG_WRITE); \
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(*(volatile uint32_t *)(_r)) = (_v); \
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})
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//read value from register
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)_r); \
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})
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
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(*(volatile uint32_t*)(_r) |= (_b)); \
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})
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
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(*(volatile uint32_t*)(_r) &= ~(_b)); \
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})
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
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(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
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})
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
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(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
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})
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) ({ \
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ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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//write value to register
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#define WRITE_PERI_REG(addr, val) ({ \
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ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
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})
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
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})
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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})
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
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(READ_PERI_REG(reg) & (mask)); \
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})
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
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((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
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})
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
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(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
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})
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
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((READ_PERI_REG(reg)>>(shift))&(mask)); \
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})
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#endif /* !__ASSEMBLER__ */
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//}}
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM ( 26*1000000 )
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ APB_CLK_FREQ
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#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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//}}
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//Interrupt hardware source table
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//This table is decided by hardware, don't touch this.
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#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
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