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RISCV-ULP: Add DS18B20 1wire RISCV-ULP example

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This commit is contained in:
Marius Vikhammer
2021-06-23 14:54:36 +08:00
parent 67743ac444
commit 386739595f
38 changed files with 369 additions and 25 deletions
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9
components/ulp/ulp_riscv/ulp_riscv_utils.c
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@@ -39,3 +39,12 @@ void ulp_riscv_shutdown(void)
while(1);
}
void ulp_riscv_delay_cycles(uint32_t cycles)
{
uint32_t start = ULP_RISCV_GET_CCOUNT();
while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) {
/* Wait */
}
}