mirror of
https://github.com/espressif/esp-idf.git
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bootloader: Enable early boot RNG entropy source
This reverts commit ceb8566970.
This commit is contained in:
Angus Gratton
@@ -158,6 +158,7 @@
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#define DR_REG_RTCMEM0_BASE 0x3ff61000
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#define DR_REG_RTCMEM1_BASE 0x3ff62000
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#define DR_REG_RTCMEM2_BASE 0x3ff63000
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#define DR_REG_SYSCON_BASE 0x3ff66000
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#define DR_REG_HINF_BASE 0x3ff4B000
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#define DR_REG_UHCI1_BASE 0x3ff4C000
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#define DR_REG_I2S_BASE 0x3ff4F000
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294
components/esp32/include/soc/syscon_reg.h
Normal file
294
components/esp32/include/soc/syscon_reg.h
Normal file
@@ -0,0 +1,294 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SYSCON_REG_H_
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#define _SOC_SYSCON_REG_H_
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#include "soc.h"
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#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
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/* SYSCON_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
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/*description: */
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#define SYSCON_QUICK_CLK_CHNG (BIT(13))
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#define SYSCON_QUICK_CLK_CHNG_M (BIT(13))
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#define SYSCON_QUICK_CLK_CHNG_V 0x1
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#define SYSCON_QUICK_CLK_CHNG_S 13
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/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: */
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#define SYSCON_RST_TICK_CNT (BIT(12))
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#define SYSCON_RST_TICK_CNT_M (BIT(12))
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#define SYSCON_RST_TICK_CNT_V 0x1
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#define SYSCON_RST_TICK_CNT_S 12
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/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
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/*description: */
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#define SYSCON_CLK_EN (BIT(11))
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#define SYSCON_CLK_EN_M (BIT(11))
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#define SYSCON_CLK_EN_V 0x1
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#define SYSCON_CLK_EN_S 11
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/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
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/*description: */
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#define SYSCON_CLK_320M_EN (BIT(10))
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#define SYSCON_CLK_320M_EN_M (BIT(10))
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#define SYSCON_CLK_320M_EN_V 0x1
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#define SYSCON_CLK_320M_EN_S 10
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/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
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/*description: */
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#define SYSCON_PRE_DIV_CNT 0x000003FF
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#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
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#define SYSCON_PRE_DIV_CNT_V 0x3FF
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#define SYSCON_PRE_DIV_CNT_S 0
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#define SYSCON_XTAL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
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/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
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/*description: */
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#define SYSCON_XTAL_TICK_NUM 0x000000FF
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#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
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#define SYSCON_XTAL_TICK_NUM_V 0xFF
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#define SYSCON_XTAL_TICK_NUM_S 0
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#define SYSCON_PLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x8)
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/* SYSCON_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */
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/*description: */
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#define SYSCON_PLL_TICK_NUM 0x000000FF
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#define SYSCON_PLL_TICK_NUM_M ((SYSCON_PLL_TICK_NUM_V)<<(SYSCON_PLL_TICK_NUM_S))
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#define SYSCON_PLL_TICK_NUM_V 0xFF
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#define SYSCON_PLL_TICK_NUM_S 0
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#define SYSCON_CK8M_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0xC)
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/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */
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/*description: */
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#define SYSCON_CK8M_TICK_NUM 0x000000FF
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#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
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#define SYSCON_CK8M_TICK_NUM_V 0xFF
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#define SYSCON_CK8M_TICK_NUM_S 0
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#define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x10)
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/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
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/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
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is from GPIO matrix*/
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#define SYSCON_SARADC_DATA_TO_I2S (BIT(26))
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#define SYSCON_SARADC_DATA_TO_I2S_M (BIT(26))
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#define SYSCON_SARADC_DATA_TO_I2S_V 0x1
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#define SYSCON_SARADC_DATA_TO_I2S_S 26
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/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
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/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
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in this case the resolution should not be larger than 11 bits.*/
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#define SYSCON_SARADC_DATA_SAR_SEL (BIT(25))
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#define SYSCON_SARADC_DATA_SAR_SEL_M (BIT(25))
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#define SYSCON_SARADC_DATA_SAR_SEL_V 0x1
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#define SYSCON_SARADC_DATA_SAR_SEL_S 25
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/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
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/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
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#define SYSCON_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
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#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
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#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V 0x1
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#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S 24
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/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
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/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
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#define SYSCON_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
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#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
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#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V 0x1
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#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S 23
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/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
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/*description: 0 ~ 15 means length 1 ~ 16*/
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#define SYSCON_SARADC_SAR2_PATT_LEN 0x0000000F
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#define SYSCON_SARADC_SAR2_PATT_LEN_M ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
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#define SYSCON_SARADC_SAR2_PATT_LEN_V 0xF
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#define SYSCON_SARADC_SAR2_PATT_LEN_S 19
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/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
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/*description: 0 ~ 15 means length 1 ~ 16*/
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#define SYSCON_SARADC_SAR1_PATT_LEN 0x0000000F
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#define SYSCON_SARADC_SAR1_PATT_LEN_M ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
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#define SYSCON_SARADC_SAR1_PATT_LEN_V 0xF
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#define SYSCON_SARADC_SAR1_PATT_LEN_S 15
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/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
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/*description: SAR clock divider*/
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#define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF
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#define SYSCON_SARADC_SAR_CLK_DIV_M ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
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#define SYSCON_SARADC_SAR_CLK_DIV_V 0xFF
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#define SYSCON_SARADC_SAR_CLK_DIV_S 7
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/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
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/*description: */
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#define SYSCON_SARADC_SAR_CLK_GATED (BIT(6))
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#define SYSCON_SARADC_SAR_CLK_GATED_M (BIT(6))
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#define SYSCON_SARADC_SAR_CLK_GATED_V 0x1
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#define SYSCON_SARADC_SAR_CLK_GATED_S 6
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/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
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/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
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#define SYSCON_SARADC_SAR_SEL (BIT(5))
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#define SYSCON_SARADC_SAR_SEL_M (BIT(5))
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#define SYSCON_SARADC_SAR_SEL_V 0x1
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#define SYSCON_SARADC_SAR_SEL_S 5
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/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
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/*description: 0: single mode 1: double mode 2: alternate mode*/
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#define SYSCON_SARADC_WORK_MODE 0x00000003
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#define SYSCON_SARADC_WORK_MODE_M ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
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#define SYSCON_SARADC_WORK_MODE_V 0x3
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#define SYSCON_SARADC_WORK_MODE_S 3
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/* SYSCON_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */
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/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled
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by PWDET CTRL*/
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#define SYSCON_SARADC_SAR2_MUX (BIT(2))
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#define SYSCON_SARADC_SAR2_MUX_M (BIT(2))
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#define SYSCON_SARADC_SAR2_MUX_V 0x1
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#define SYSCON_SARADC_SAR2_MUX_S 2
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/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
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/*description: */
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#define SYSCON_SARADC_START (BIT(1))
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#define SYSCON_SARADC_START_M (BIT(1))
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#define SYSCON_SARADC_START_V 0x1
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#define SYSCON_SARADC_START_S 1
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/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: */
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#define SYSCON_SARADC_START_FORCE (BIT(0))
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#define SYSCON_SARADC_START_FORCE_M (BIT(0))
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#define SYSCON_SARADC_START_FORCE_V 0x1
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#define SYSCON_SARADC_START_FORCE_S 0
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#define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x14)
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/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
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/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
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#define SYSCON_SARADC_SAR2_INV (BIT(10))
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#define SYSCON_SARADC_SAR2_INV_M (BIT(10))
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#define SYSCON_SARADC_SAR2_INV_V 0x1
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#define SYSCON_SARADC_SAR2_INV_S 10
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/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
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/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
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#define SYSCON_SARADC_SAR1_INV (BIT(9))
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#define SYSCON_SARADC_SAR1_INV_M (BIT(9))
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#define SYSCON_SARADC_SAR1_INV_V 0x1
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#define SYSCON_SARADC_SAR1_INV_S 9
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/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
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/*description: max conversion number*/
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#define SYSCON_SARADC_MAX_MEAS_NUM 0x000000FF
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#define SYSCON_SARADC_MAX_MEAS_NUM_M ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
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#define SYSCON_SARADC_MAX_MEAS_NUM_V 0xFF
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#define SYSCON_SARADC_MAX_MEAS_NUM_S 1
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/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: */
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#define SYSCON_SARADC_MEAS_NUM_LIMIT (BIT(0))
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#define SYSCON_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
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#define SYSCON_SARADC_MEAS_NUM_LIMIT_V 0x1
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#define SYSCON_SARADC_MEAS_NUM_LIMIT_S 0
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#define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x18)
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/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
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/*description: sample cycles*/
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#define SYSCON_SARADC_SAMPLE_CYCLE 0x000000FF
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#define SYSCON_SARADC_SAMPLE_CYCLE_M ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
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#define SYSCON_SARADC_SAMPLE_CYCLE_V 0xFF
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#define SYSCON_SARADC_SAMPLE_CYCLE_S 24
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/* SYSCON_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */
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/*description: */
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#define SYSCON_SARADC_START_WAIT 0x000000FF
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#define SYSCON_SARADC_START_WAIT_M ((SYSCON_SARADC_START_WAIT_V)<<(SYSCON_SARADC_START_WAIT_S))
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#define SYSCON_SARADC_START_WAIT_V 0xFF
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#define SYSCON_SARADC_START_WAIT_S 16
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/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */
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/*description: */
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#define SYSCON_SARADC_STANDBY_WAIT 0x000000FF
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#define SYSCON_SARADC_STANDBY_WAIT_M ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
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#define SYSCON_SARADC_STANDBY_WAIT_V 0xFF
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#define SYSCON_SARADC_STANDBY_WAIT_S 8
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/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
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/*description: */
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#define SYSCON_SARADC_RSTB_WAIT 0x000000FF
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#define SYSCON_SARADC_RSTB_WAIT_M ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
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#define SYSCON_SARADC_RSTB_WAIT_V 0xFF
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#define SYSCON_SARADC_RSTB_WAIT_S 0
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#define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x1C)
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/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
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/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
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#define SYSCON_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB1_M ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
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#define SYSCON_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB1_S 0
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#define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x20)
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/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
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/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
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#define SYSCON_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB2_M ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
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#define SYSCON_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB2_S 0
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#define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x24)
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/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
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/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
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#define SYSCON_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB3_M ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
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#define SYSCON_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB3_S 0
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#define SYSCON_SARADC_SAR1_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x28)
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/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
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/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
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#define SYSCON_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB4_M ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
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#define SYSCON_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
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#define SYSCON_SARADC_SAR1_PATT_TAB4_S 0
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#define SYSCON_SARADC_SAR2_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x2C)
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/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
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/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
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#define SYSCON_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
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#define SYSCON_SARADC_SAR2_PATT_TAB1_M ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
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#define SYSCON_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
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#define SYSCON_SARADC_SAR2_PATT_TAB1_S 0
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#define SYSCON_SARADC_SAR2_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x30)
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/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
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/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
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#define SYSCON_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB2_M ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB2_S 0
|
||||
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x34)
|
||||
/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
|
||||
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB3_M ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB3_S 0
|
||||
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x38)
|
||||
/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
|
||||
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB4_M ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
|
||||
#define SYSCON_SARADC_SAR2_PATT_TAB4_S 0
|
||||
|
||||
#define SYSCON_APLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x3C)
|
||||
/* SYSCON_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */
|
||||
/*description: */
|
||||
#define SYSCON_APLL_TICK_NUM 0x000000FF
|
||||
#define SYSCON_APLL_TICK_NUM_M ((SYSCON_APLL_TICK_NUM_V)<<(SYSCON_APLL_TICK_NUM_S))
|
||||
#define SYSCON_APLL_TICK_NUM_V 0xFF
|
||||
#define SYSCON_APLL_TICK_NUM_S 0
|
||||
|
||||
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x7C)
|
||||
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
|
||||
/*description: */
|
||||
#define SYSCON_DATE 0xFFFFFFFF
|
||||
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
|
||||
#define SYSCON_DATE_V 0xFFFFFFFF
|
||||
#define SYSCON_DATE_S 0
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SYSCON_REG_H_ */
|
||||
|
||||
|
||||
120
components/esp32/include/soc/syscon_struct.h
Normal file
120
components/esp32/include/soc/syscon_struct.h
Normal file
@@ -0,0 +1,120 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SYSCON_STRUCT_H_
|
||||
#define _SOC_SYSCON_STRUCT_H_
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t pre_div: 10;
|
||||
volatile uint32_t clk_320m_en: 1;
|
||||
volatile uint32_t clk_en: 1;
|
||||
volatile uint32_t rst_tick: 1;
|
||||
volatile uint32_t quick_clk_chng: 1;
|
||||
volatile uint32_t reserved14: 18;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}clk_conf;
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t xtal_tick: 8;
|
||||
volatile uint32_t reserved8: 24;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}xtal_tick_conf;
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t pll_tick: 8;
|
||||
volatile uint32_t reserved8: 24;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}pll_tick_conf;
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t ck8m_tick: 8;
|
||||
volatile uint32_t reserved8: 24;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}ck8m_tick_conf;
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t start_force: 1;
|
||||
volatile uint32_t start: 1;
|
||||
volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/
|
||||
volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
|
||||
volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
|
||||
volatile uint32_t sar_clk_gated: 1;
|
||||
volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/
|
||||
volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
|
||||
volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
|
||||
volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
|
||||
volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
|
||||
volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
|
||||
volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
|
||||
volatile uint32_t reserved27: 5;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}saradc_ctrl;
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t meas_num_limit: 1;
|
||||
volatile uint32_t max_meas_num: 8; /*max conversion number*/
|
||||
volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
|
||||
volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
|
||||
volatile uint32_t reserved11: 21;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}saradc_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t rstb_wait: 8;
|
||||
volatile uint32_t standby_wait: 8;
|
||||
volatile uint32_t start_wait: 8;
|
||||
volatile uint32_t sample_cycle: 8; /*sample cycles*/
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}saradc_fsm;
|
||||
volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
|
||||
volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
|
||||
union {
|
||||
struct {
|
||||
volatile uint32_t apll_tick: 8;
|
||||
volatile uint32_t reserved8: 24;
|
||||
};
|
||||
volatile uint32_t val;
|
||||
}apll_tick_conf;
|
||||
volatile uint32_t reserved_40;
|
||||
volatile uint32_t reserved_44;
|
||||
volatile uint32_t reserved_48;
|
||||
volatile uint32_t reserved_4c;
|
||||
volatile uint32_t reserved_50;
|
||||
volatile uint32_t reserved_54;
|
||||
volatile uint32_t reserved_58;
|
||||
volatile uint32_t reserved_5c;
|
||||
volatile uint32_t reserved_60;
|
||||
volatile uint32_t reserved_64;
|
||||
volatile uint32_t reserved_68;
|
||||
volatile uint32_t reserved_6c;
|
||||
volatile uint32_t reserved_70;
|
||||
volatile uint32_t reserved_74;
|
||||
volatile uint32_t reserved_78;
|
||||
volatile uint32_t date; /**/
|
||||
} syscon_dev_t;
|
||||
|
||||
#endif /* _SOC_SYSCON_STRUCT_H_ */
|
||||
Reference in New Issue
Block a user