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Fixed ESP32 EMAC driver insufficient TX buffer size which could followed esp_eth_stop and esp_eth_start sequence
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@@ -184,6 +184,8 @@ void emac_hal_reset_desc_chain(emac_hal_context_t *hal)
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/* init tx chain */
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for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
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/* Set Own bit of the Tx descriptor Status: CPU */
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hal->tx_desc[i].TDES0.Own = 0;
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/* Set Second Address Chained bit */
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hal->tx_desc[i].TDES0.SecondAddressChained = 1;
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hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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@@ -427,27 +429,34 @@ void emac_hal_start(emac_hal_context_t *hal)
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hal->dma_regs->dmastatus.val = 0xFFFFFFFF;
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}
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void emac_hal_stop(emac_hal_context_t *hal)
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esp_err_t emac_hal_stop(emac_hal_context_t *hal)
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{
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typeof(hal->dma_regs->dmaoperation_mode) opm = hal->dma_regs->dmaoperation_mode;
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typeof(hal->mac_regs->gmacconfig) cfg = hal->mac_regs->gmacconfig;
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/* Flush Transmit FIFO */
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opm.flush_tx_fifo = 1;
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/* Stop DMA transmission */
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opm.start_stop_transmission_command = 0;
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/* Stop DMA reception */
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opm.start_stop_rx = 0;
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hal->dma_regs->dmaoperation_mode = opm;
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if (hal->mac_regs->emacdebug.mactfcs != 0x0) {
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/* Previous transmit in progress */
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return ESP_ERR_INVALID_STATE;
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}
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/* Disable receive state machine of the MAC for reception from the MII */
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cfg.rx = 0;
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/* Disable transmit state machine of the MAC for transmission on the MII */
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cfg.tx = 0;
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hal->dma_regs->dmaoperation_mode = opm;
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hal->mac_regs->gmacconfig = cfg;
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/* Disable Ethernet MAC and DMA Interrupt */
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hal->dma_regs->dmain_en.val = 0x0;
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return ESP_OK;
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}
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uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal)
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