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	Fixed ESP32 EMAC driver insufficient TX buffer size which could followed esp_eth_stop and esp_eth_start sequence
				
					
				
			This commit is contained in:
		| @@ -323,6 +323,13 @@ esp_err_t esp_eth_transmit(esp_eth_handle_t hdl, void *buf, size_t length) | ||||
| { | ||||
|     esp_err_t ret = ESP_OK; | ||||
|     esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl; | ||||
|  | ||||
|     if (atomic_load(ð_driver->fsm) != ESP_ETH_FSM_START) { | ||||
|         ret = ESP_ERR_INVALID_STATE; | ||||
|         ESP_LOGD(TAG, "Ethernet is not started"); | ||||
|         goto err; | ||||
|     } | ||||
|  | ||||
|     ETH_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG); | ||||
|     ETH_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG); | ||||
|     ETH_CHECK(eth_driver, "ethernet driver handle can't be null", err, ESP_ERR_INVALID_ARG); | ||||
|   | ||||
| @@ -47,7 +47,7 @@ static const char *TAG = "emac_esp32"; | ||||
|     } while (0) | ||||
|  | ||||
| #define PHY_OPERATION_TIMEOUT_US (1000) | ||||
|  | ||||
| #define MAC_STOP_TIMEOUT_MS (100) | ||||
| #define FLOW_CONTROL_LOW_WATER_MARK (CONFIG_ETH_DMA_RX_BUFFER_NUM / 3) | ||||
| #define FLOW_CONTROL_HIGH_WATER_MARK (FLOW_CONTROL_LOW_WATER_MARK * 2) | ||||
|  | ||||
| @@ -388,6 +388,7 @@ static esp_err_t emac_esp32_deinit(esp_eth_mac_t *mac) | ||||
| static esp_err_t emac_esp32_start(esp_eth_mac_t *mac) | ||||
| { | ||||
|     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent); | ||||
|     emac_hal_reset_desc_chain(&emac->hal); | ||||
|     emac_hal_start(&emac->hal); | ||||
|     return ESP_OK; | ||||
| } | ||||
| @@ -395,8 +396,16 @@ static esp_err_t emac_esp32_start(esp_eth_mac_t *mac) | ||||
| static esp_err_t emac_esp32_stop(esp_eth_mac_t *mac) | ||||
| { | ||||
|     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent); | ||||
|     emac_hal_stop(&emac->hal); | ||||
|     return ESP_OK; | ||||
|     esp_err_t ret = ESP_OK; | ||||
|     int32_t to = 0; | ||||
|     do { | ||||
|         if ((ret = emac_hal_stop(&emac->hal)) == ESP_OK) { | ||||
|             break; | ||||
|         } | ||||
|         to += 20; | ||||
|         vTaskDelay(pdMS_TO_TICKS(20)); | ||||
|     } while (to < MAC_STOP_TIMEOUT_MS); | ||||
|     return ret; | ||||
| } | ||||
|  | ||||
| static esp_err_t emac_esp32_del(esp_eth_mac_t *mac) | ||||
|   | ||||
| @@ -184,6 +184,8 @@ void emac_hal_reset_desc_chain(emac_hal_context_t *hal) | ||||
|  | ||||
|     /* init tx chain */ | ||||
|     for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) { | ||||
|         /* Set Own bit of the Tx descriptor Status: CPU */ | ||||
|         hal->tx_desc[i].TDES0.Own = 0; | ||||
|         /* Set Second Address Chained bit */ | ||||
|         hal->tx_desc[i].TDES0.SecondAddressChained = 1; | ||||
|         hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE; | ||||
| @@ -427,27 +429,34 @@ void emac_hal_start(emac_hal_context_t *hal) | ||||
|     hal->dma_regs->dmastatus.val = 0xFFFFFFFF; | ||||
| } | ||||
|  | ||||
| void emac_hal_stop(emac_hal_context_t *hal) | ||||
| esp_err_t emac_hal_stop(emac_hal_context_t *hal) | ||||
| { | ||||
|     typeof(hal->dma_regs->dmaoperation_mode) opm = hal->dma_regs->dmaoperation_mode; | ||||
|     typeof(hal->mac_regs->gmacconfig) cfg = hal->mac_regs->gmacconfig; | ||||
|  | ||||
|     /* Flush Transmit FIFO */ | ||||
|     opm.flush_tx_fifo = 1; | ||||
|     /* Stop DMA transmission */ | ||||
|     opm.start_stop_transmission_command = 0; | ||||
|     /* Stop DMA reception */ | ||||
|     opm.start_stop_rx = 0; | ||||
|  | ||||
|     hal->dma_regs->dmaoperation_mode = opm; | ||||
|  | ||||
|     if (hal->mac_regs->emacdebug.mactfcs != 0x0) { | ||||
|         /* Previous transmit in progress */ | ||||
|         return ESP_ERR_INVALID_STATE; | ||||
|     } | ||||
|  | ||||
|     /* Disable receive state machine of the MAC for reception from the MII */ | ||||
|     cfg.rx = 0; | ||||
|     /* Disable transmit state machine of the MAC for transmission on the MII */ | ||||
|     cfg.tx = 0; | ||||
|  | ||||
|     hal->dma_regs->dmaoperation_mode = opm; | ||||
|     hal->mac_regs->gmacconfig = cfg; | ||||
|  | ||||
|     /* Disable Ethernet MAC and DMA Interrupt */ | ||||
|     hal->dma_regs->dmain_en.val = 0x0; | ||||
|  | ||||
|     return ESP_OK; | ||||
| } | ||||
|  | ||||
| uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal) | ||||
|   | ||||
| @@ -1,16 +1,8 @@ | ||||
| // Copyright 2019 Espressif Systems (Shanghai) PTE LTD | ||||
| // | ||||
| // Licensed under the Apache License, Version 2.0 (the "License"); | ||||
| // you may not use this file except in compliance with the License. | ||||
| // You may obtain a copy of the License at | ||||
| // | ||||
| //     http://www.apache.org/licenses/LICENSE-2.0 | ||||
| // | ||||
| // Unless required by applicable law or agreed to in writing, software | ||||
| // distributed under the License is distributed on an "AS IS" BASIS, | ||||
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||||
| // See the License for the specific language governing permissions and | ||||
| // limitations under the License. | ||||
| /* | ||||
|  * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD | ||||
|  * | ||||
|  * SPDX-License-Identifier: Apache-2.0 | ||||
|  */ | ||||
|  | ||||
| #pragma once | ||||
|  | ||||
| @@ -381,9 +373,24 @@ uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal); | ||||
|  | ||||
| void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr); | ||||
|  | ||||
|  | ||||
| /** | ||||
|  * @brief Starts EMAC Transmission & Reception | ||||
|  * | ||||
|  * @param hal EMAC HAL context infostructure | ||||
|  */ | ||||
| void emac_hal_start(emac_hal_context_t *hal); | ||||
|  | ||||
| void emac_hal_stop(emac_hal_context_t *hal); | ||||
| /** | ||||
|  * @brief Stops EMAC Transmission & Reception | ||||
|  * | ||||
|  * @param hal EMAC HAL context infostructure | ||||
|  * @return | ||||
|  *     - ESP_OK: succeed | ||||
|   *    - ESP_ERR_INVALID_STATE: previous frame transmission is not completed. When this error occurs, | ||||
|   *      wait and reapeat the EMAC stop again. | ||||
|  */ | ||||
| esp_err_t emac_hal_stop(emac_hal_context_t *hal); | ||||
|  | ||||
| uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal); | ||||
|  | ||||
|   | ||||
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	 Ondrej Kosta
					Ondrej Kosta