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fix(i2c): Fix possible error state in clear the bus,

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Closes https://github.com/espressif/esp-idf/issues/13647
This commit is contained in:
C.S.M
2024-08-28 18:21:28 +08:00
parent 9ec1042dff
commit 3ccdd8b397
12 changed files with 190 additions and 54 deletions
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21
components/hal/esp32c6/include/hal/i2c_ll.h
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@@ -754,18 +754,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**