diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 161d58e07c..49340b27be 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -130,7 +130,7 @@ __attribute__((weak)) void bootloader_clock_configure(void) CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */ // SET CLR SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */ - SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */ + // SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */ // TODOļ¼š workaround for FIB chip, uncomment on MP version. SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */ SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */ SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR); diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h index d97daa87ba..e72580f897 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h @@ -126,6 +126,19 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { }; #define TEST_RTCIO_INTR_PIN_INDEX 5 // IO12 #define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO12 +#elif CONFIG_IDF_TARGET_ESP32H21 +#define TEST_GPIO_PIN_COUNT 7 +const int s_test_map[TEST_GPIO_PIN_COUNT] = { + GPIO_NUM_5, //GPIO5 + GPIO_NUM_6, //GPIO6 + GPIO_NUM_7, //GPIO7 + GPIO_NUM_8, //GPIO8 + GPIO_NUM_9, //GPIO9 + GPIO_NUM_10, //GPIO10 + GPIO_NUM_11, //GPIO11 +}; +#define TEST_RTCIO_INTR_PIN_INDEX 6 // IO11 +#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 6 // IO11 #elif CONFIG_IDF_TARGET_ESP32P4 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index 4e5782dcf4..fcf21670b9 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -349,7 +349,7 @@ static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module) #define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP)) #define ICG_NOGATING_MODEM (BIT(PMU_HP_ICG_MODEM_CODE_MODEM)) -#if !CONFIG_IDF_TARGET_ESP32H2 +#if SOC_PM_SUPPORT_PMU_MODEM_STATE static const DRAM_ATTR uint32_t initial_gating_mode[MODEM_CLOCK_DOMAIN_MAX] = { [MODEM_CLOCK_DOMAIN_MODEM_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, [MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ICG_NOGATING_ACTIVE, @@ -364,7 +364,7 @@ static const DRAM_ATTR uint32_t initial_gating_mode[MODEM_CLOCK_DOMAIN_MAX] = { }; #endif -#if !CONFIG_IDF_TARGET_ESP32H2 //TODO: PM-92 +#if SOC_PM_SUPPORT_PMU_MODEM_STATE static IRAM_ATTR void modem_clock_module_icg_map_init_all(void) { esp_os_enter_critical_safe(&MODEM_CLOCK_instance()->lock); @@ -379,7 +379,7 @@ static IRAM_ATTR void modem_clock_module_icg_map_init_all(void) void IRAM_ATTR modem_clock_module_enable(periph_module_t module) { assert(IS_MODEM_MODULE(module)); -#if !CONFIG_IDF_TARGET_ESP32H2 +#if SOC_PM_SUPPORT_PMU_MODEM_STATE modem_clock_module_icg_map_init_all(); #endif uint32_t deps = modem_clock_get_module_deps(module); diff --git a/components/esp_hw_support/port/esp32h21/pmu_init.c b/components/esp_hw_support/port/esp32h21/pmu_init.c index 4a9f8d96f7..5ec242300f 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_init.c +++ b/components/esp_hw_support/port/esp32h21/pmu_init.c @@ -194,6 +194,7 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx) { assert(ctx); for (pmu_hp_mode_t mode = PMU_MODE_HP_ACTIVE; mode < PMU_MODE_HP_MAX; mode++) { + if (mode == PMU_MODE_HP_MODEM) continue; pmu_hp_system_analog_param_t analog = {}; pmu_hp_system_param_t param = {.analog = &analog}; @@ -247,13 +248,10 @@ void pmu_init() pmu_hp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance()); + pmu_ll_dcm_ctrl_ccm_sw_en(&PMU, true); pmu_power_domain_force_default(PMU_instance()); - // default ccm mode - REG_SET_FIELD(PMU_DCM_CTRL_REG, PMU_DCDC_CCM_SW_EN, 1); - REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCDC_CCM_ENB, 0); - #if !CONFIG_IDF_ENV_FPGA // TODO: IDF-11548 // if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { diff --git a/components/esp_hw_support/port/esp32h21/pmu_param.c b/components/esp_hw_support/port/esp32h21/pmu_param.c index 391bc9060e..fd5173b28c 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_param.c +++ b/components/esp_hw_support/port/esp32h21/pmu_param.c @@ -39,29 +39,6 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .xpd_bbpll_i2c = 1, \ .xpd_bbpll = 1 \ }, \ - .xtal = { \ - .xpd_xtalx2 = 1, \ - .xpd_xtal = 1 \ - } \ -} - -#define PMU_HP_MODEM_POWER_CONFIG_DEFAULT() { \ - .dig_power = { \ - .vdd_flash_mode = 0, \ - .mem_dslp = 1, \ - .mem_pd_en = 0, \ - .wifi_pd_en = 0, \ - .cpu_pd_en = 1, \ - .aon_pd_en = 0, \ - .top_pd_en = 0 \ - }, \ - .clk_power = { \ - .i2c_iso_en = 0, \ - .i2c_retention = 0, \ - .xpd_bb_i2c = 1, \ - .xpd_bbpll_i2c = 1, \ - .xpd_bbpll = 1 \ - }, \ .xtal = { \ .xpd_xtalx2 = 0, \ .xpd_xtal = 1 \ @@ -70,7 +47,7 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); #define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ - .vdd_flash_mode = 1, \ + .vdd_flash_mode = 0, \ .mem_dslp = 0, \ .mem_pd_en = 0, \ .wifi_pd_en = 1, \ @@ -95,7 +72,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod { static const pmu_hp_system_power_param_t hp_power[] = { PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(), - PMU_HP_MODEM_POWER_CONFIG_DEFAULT(), + {{}, {}, {}}, // No Modem State PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() }; assert(mode < ARRAY_SIZE(hp_power)); @@ -105,9 +82,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod #define PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT() { \ .icg_func = 0xffffffff, \ .icg_apb = 0xffffffff, \ - .icg_modem = { \ - .code = PMU_HP_ICG_MODEM_CODE_ACTIVE \ - }, \ + .icg_modem = {}, \ .sysclk = { \ .dig_sysclk_nodiv = 0, \ .icg_sysclk_en = 1, \ @@ -117,27 +92,10 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod } \ } -#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() { \ - .icg_func = 0, \ - .icg_apb = 0, \ - .icg_modem = { \ - .code = PMU_HP_ICG_MODEM_CODE_MODEM \ - }, \ - .sysclk = { \ - .dig_sysclk_nodiv = 0, \ - .icg_sysclk_en = 1, \ - .sysclk_slp_sel = 1, \ - .icg_slp_sel = 1, \ - .dig_sysclk_sel = SOC_CPU_CLK_SRC_PLL \ - } \ -} - #define PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() { \ .icg_func = 0, \ .icg_apb = 0, \ - .icg_modem = { \ - .code = PMU_HP_ICG_MODEM_CODE_SLEEP \ - }, \ + .icg_modem = {}, \ .sysclk = { \ .dig_sysclk_nodiv = 0, \ .icg_sysclk_en = 0, \ @@ -151,7 +109,7 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod { static const pmu_hp_system_clock_param_t hp_clock[] = { PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(), - PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT(), + {0, 0, {}, {}}, // No Modem State PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() }; assert(mode < ARRAY_SIZE(hp_clock)); @@ -169,17 +127,6 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod } \ } -#define PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT() { \ - .syscntl = { \ - .uart_wakeup_en = 1, \ - .lp_pad_hold_all = 0, \ - .hp_pad_hold_all = 0, \ - .dig_pad_slp_sel = 1, \ - .dig_pause_wdt = 1, \ - .dig_cpu_stall = 1 \ - } \ -} - #define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \ .syscntl = { \ .uart_wakeup_en = 1, \ @@ -195,7 +142,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp { static const pmu_hp_system_digital_param_t hp_digital[] = { PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(), - PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT(), + {{}}, // No Modem State, PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() }; assert(mode < ARRAY_SIZE(hp_digital)); @@ -204,12 +151,12 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp #define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \ .bias = { \ - .dcdc_ccm_enb = 1, \ + .dcdc_ccm_enb = 0, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 2, \ .dig_reg_dsfmos = 10, \ - .dcm_vset = 22, \ - .dcm_mode = 2, \ + .dcm_vset = 24, \ + .dcm_mode = 3, \ .xpd_trx = 1, \ .xpd_bias = 1, \ .discnnt_dig_rtc = 0, \ @@ -234,34 +181,6 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp } \ } -#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .dcdc_ccm_enb = 1, \ - .dcdc_clear_rdy = 0, \ - .dig_reg_dpcur_bias = 3, \ - .dig_reg_dsfmos = 12, \ - .dcm_vset = 20, \ - .dcm_mode = 1, \ - .xpd_trx = 1, \ - .xpd_bias = 1, \ - .discnnt_dig_rtc = 0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ - }, \ - .regulator0 = { \ - .power_det_bypass = 0, \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = HP_CALI_DBIAS_DEFAULT \ - }, \ - .regulator1 = { \ - .drv_b = 0x1b \ - } \ -} - #define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ .bias = { \ .dcdc_ccm_enb = 1, \ @@ -269,7 +188,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 8, \ .dcm_vset = 0, \ - .dcm_mode = 0, \ + .dcm_mode = 3, \ .xpd_trx = 0, \ .xpd_bias = 0, \ .discnnt_dig_rtc = 0, \ @@ -286,7 +205,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .dbias = 0 \ }, \ .regulator1 = { \ - .drv_b = 0x13 \ + .drv_b = 26 \ } \ } @@ -294,7 +213,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m { static const pmu_hp_system_analog_param_t hp_analog[] = { PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(), - PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT(), + {{}, {}, {}}, // No modem state PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() }; assert(mode < ARRAY_SIZE(hp_analog)); @@ -317,16 +236,6 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .backup_clk = 0xffffffff, \ } -#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ - .retention = { \ - .hp_sleep2modem_backup_modem_clk_code = 3, \ - .hp_sleep2modem_backup_clk_sel = 0, \ - .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ - .hp_sleep2modem_backup_en = 0, \ - }, \ - .backup_clk = 0xffffffff, \ -} - #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ .retention = { \ .hp_modem2sleep_backup_modem_clk_code = 3, \ @@ -345,7 +254,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm { static const pmu_hp_system_retention_param_t hp_retention[] = { PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(), - PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT(), + {{}, 0}, // No Modem PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() }; assert(mode < ARRAY_SIZE(hp_retention)); @@ -356,7 +265,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm /** LP system default parameter */ #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ - .vdd_io_mode = 3, \ + .vdd_io_mode = 4, \ .bod_source_sel = 0, \ .vddbat_mode = 2, \ .mem_dslp = 0, \ @@ -365,7 +274,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm .clk_power = { \ .xpd_lppll = 0, \ .xpd_xtal32k = 1, \ - .xpd_rc32k = 1, \ + .xpd_rc32k = 0, \ .xpd_fosc = 1, \ .pd_osc = 0 \ } \ @@ -373,7 +282,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm #define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ - .vdd_io_mode = 5, \ + .vdd_io_mode = 3, \ .bod_source_sel = 0, \ .vddbat_mode = 1, \ .mem_dslp = 1, \ @@ -416,12 +325,12 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod #define PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ .bias = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 3, \ .dig_reg_dsfmos = 5, \ .dcm_vset = 0, \ - .dcm_mode = 0, \ + .dcm_mode = 3, \ .xpd_bias = 0, \ .discnnt_dig_rtc = 0, \ .pd_cur = 1, \ @@ -434,7 +343,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod .dbias = 1 \ }, \ .regulator1 = { \ - .drv_b = 9 \ + .drv_b = 0 \ } \ } diff --git a/components/esp_hw_support/port/esp32h21/pmu_sleep.c b/components/esp_hw_support/port/esp32h21/pmu_sleep.c index 29606fb43e..ef3a39c7b8 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h21/pmu_sleep.c @@ -79,17 +79,14 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk /* HP core hardware wait time, microsecond */ const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us; - if (sleep_flags & PMU_SLEEP_PD_TOP) { - mc->hp.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US; - } else { - mc->hp.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US; - } - const int hp_regdma_wait_time_us = mc->hp.regdma_s2a_work_time_us; + const int hp_control_wait_time_us = mc->hp.isolate_wait_time_us + mc->hp.reset_wait_time_us; + const int hp_regdma_wait_time_us = s_pmu_sleep_regdma_backup_enabled ? mc->hp.regdma_s2a_work_time_us : 0; /* If XTAL is not used as RTC_FAST clock source, it is started in HP_SLEEP -> HP_ACTIVE stage and the clock waiting time is counted into hp_hw_wait_time */ const int hp_clock_wait_time_us = ((sleep_flags & PMU_SLEEP_PD_XTAL) && !(sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST)) \ ? mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us \ : mc->hp.pll_wait_stable_time_us; - const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us + hp_clock_wait_time_us; + const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + hp_digital_power_up_wait_time_us + hp_clock_wait_time_us \ + + hp_regdma_wait_time_us + hp_control_wait_time_us; const int rf_on_protect_time_us = 0; const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us; @@ -115,11 +112,15 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default( param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period); param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period); param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period); + param->hp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period); + param->hp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period); param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period); param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period); param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period); param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period); + param->lp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->lp.isolate_wait_time_us, fastclk_period); + param->lp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->lp.reset_wait_time_us, fastclk_period); if (power->hp_sys.xtal.xpd_xtal) { param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period); @@ -204,19 +205,21 @@ static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_c static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp) { assert(ctx->hal); - pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); - pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); - pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); - pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); - pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); - pmu_ll_hp_set_trx_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd_trx); - pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); - pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep); - pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd); - pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd); - pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias); - pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias); - pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b); + pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); + pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); + pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); + pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); + pmu_ll_hp_set_trx_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd_trx); + pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); + pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep); + pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd); + pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd); + pmu_ll_lp_set_regulator_sleep_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias); + pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias); + pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b); + pmu_ll_lp_set_dcm_vset (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dcm_vset); + pmu_ll_lp_set_dcm_mode (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dcm_mode); } static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp) diff --git a/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h index 502b0e6edb..b3c44c0a8d 100644 --- a/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h @@ -41,9 +41,7 @@ extern "C" { #define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 1 #define PMU_LP_DBIAS_SLEEP_0V7_DEFAULT 6 -#define PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US 0 -// The current value of this depends on the restoration time overhead of the longest chain in regdma -#define PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US 390 +#define PMU_REGDMA_S2A_WORK_TIME_US 390 // FOR DEEPSLEEP #define PMU_HP_XPD_DEEPSLEEP 0 @@ -288,7 +286,7 @@ typedef struct { #define PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags) { \ .hp_sys = { \ .dig_power = { \ - .vdd_flash_mode = 3, \ + .vdd_flash_mode = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 3, \ .wifi_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0,\ .cpu_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0,\ .top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0,\ @@ -309,7 +307,7 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_ACTIVE] = { \ .dig_power = { \ - .vdd_io_mode = 5, \ + .vdd_io_mode = 4, \ .bod_source_sel = 0, \ .vddbat_mode = 0, \ .peri_pd_en = 0, \ @@ -324,7 +322,7 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .dig_power = { \ - .vdd_io_mode = 11, \ + .vdd_io_mode = 4, \ .bod_source_sel = 0, \ .vddbat_mode = 1, \ .peri_pd_en = ((sleep_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0,\ @@ -381,7 +379,7 @@ typedef struct { .dig_reg_dpcur_bias = 2, \ .dig_reg_dsfmos = 10, \ .dcm_vset = 29, \ - .dcm_mode = 2, \ + .dcm_mode = 3, \ .xpd_trx = PMU_XPD_TRX_SLEEP_DEFAULT, \ .xpd_bias = 1, \ .discnnt_dig_rtc = 0, \ @@ -408,15 +406,15 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 0, \ .dig_reg_dsfmos = 0, \ .dcm_vset = 0, \ - .dcm_mode = 0, \ + .dcm_mode = 3, \ .xpd_bias = 1, \ .discnnt_dig_rtc = 1, \ - .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ + .drv_b = PMU_LP_DRVB_LIGHTSLEEP, \ .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ @@ -430,12 +428,12 @@ typedef struct { #define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags) { \ .hp_sys = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 0, \ .dig_reg_dsfmos = 5, \ .dcm_vset = 10, \ - .dcm_mode = 0, \ + .dcm_mode = 3, \ .xpd_trx = PMU_XPD_TRX_SLEEP_DEFAULT, \ .xpd_bias = 0, \ .discnnt_dig_rtc = 0, \ @@ -462,12 +460,12 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 0, \ .dig_reg_dsfmos = 0, \ .dcm_vset = 0, \ - .dcm_mode = 0, \ + .dcm_mode = 3, \ .xpd_bias = 1, \ .discnnt_dig_rtc = 1, \ .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ @@ -543,7 +541,7 @@ typedef struct pmu_sleep_machine_constant { #define PMU_SLEEP_MC_DEFAULT() { \ .lp = { \ .min_slp_time_us = 450, \ - .analog_wait_time_us = 154, \ + .analog_wait_time_us = 100, \ .xtal_wait_stable_time_us = 250, \ .clk_switch_cycle = 1, \ .clk_power_on_wait_cycle = 1, \ @@ -554,13 +552,13 @@ typedef struct pmu_sleep_machine_constant { }, \ .hp = { \ .min_slp_time_us = 450, \ - .analog_wait_time_us = 154, \ + .analog_wait_time_us = 1600, \ .isolate_wait_time_us = 1, \ .reset_wait_time_us = 1, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ - .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US, \ - .regdma_a2s_work_time_us = 0, \ + .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \ + .regdma_a2s_work_time_us = 190, \ .xtal_wait_stable_time_us = 250, \ .pll_wait_stable_time_us = 1 \ } \ diff --git a/components/esp_hw_support/port/esp32h21/rtc_time.c b/components/esp_hw_support/port/esp32h21/rtc_time.c index c39aadbc79..efab69011b 100644 --- a/components/esp_hw_support/port/esp32h21/rtc_time.c +++ b/components/esp_hw_support/port/esp32h21/rtc_time.c @@ -205,10 +205,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) uint64_t rtc_time_get(void) { - ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet"); - return 0; - // TODO: [ESP32H21] IDF-11512 - // return lp_timer_hal_get_cycle_count(); + return lp_timer_hal_get_cycle_count(); } uint32_t rtc_clk_freq_cal(uint32_t cal_val) diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c index 837048983b..259f822234 100644 --- a/components/esp_hw_support/sleep_modem.c +++ b/components/esp_hw_support/sleep_modem.c @@ -195,7 +195,7 @@ inline __attribute__((always_inline)) bool sleep_modem_wifi_modem_link_done(void bool modem_domain_pd_allowed(void) { -#if SOC_PM_MODEM_RETENTION_BY_REGDMA +#if SOC_PM_MODEM_RETENTION_BY_REGDMA && SOC_PAU_SUPPORTED const sleep_retention_module_bitmap_t inited_modules = sleep_retention_get_inited_modules(); const sleep_retention_module_bitmap_t created_modules = sleep_retention_get_created_modules(); diff --git a/components/esp_system/port/soc/esp32h21/clk.c b/components/esp_system/port/soc/esp32h21/clk.c index 4f1e99ecd8..8692ea17f4 100644 --- a/components/esp_system/port/soc/esp32h21/clk.c +++ b/components/esp_system/port/soc/esp32h21/clk.c @@ -185,5 +185,10 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { + soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); + esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t)(\ + (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ + : ESP_PD_DOMAIN_MAX); + esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); } diff --git a/components/hal/esp32h21/include/hal/lp_aon_ll.h b/components/hal/esp32h21/include/hal/lp_aon_ll.h index 038fa4d15a..c92520178b 100644 --- a/components/hal/esp32h21/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h21/include/hal/lp_aon_ll.h @@ -79,7 +79,6 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp) { if (dslp) { REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */ - } else { REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ } diff --git a/components/hal/esp32h21/include/hal/pmu_ll.h b/components/hal/esp32h21/include/hal/pmu_ll.h index eb6f838621..22aaf1f259 100644 --- a/components/hal/esp32h21/include/hal/pmu_ll.h +++ b/components/hal/esp32h21/include/hal/pmu_ll.h @@ -714,6 +714,11 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t * return hw->power.wait_timer0.powerup_timer; } +FORCE_INLINE_ATTR void pmu_ll_dcm_ctrl_ccm_sw_en(pmu_dev_t *hw, bool enable) +{ + hw->dcm_ctrl.dcdc_ccm_sw_en = enable; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index 5b12545ccb..e5dfd7dcf5 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -24,7 +24,7 @@ typedef struct { modem_lpcon_dev_t *lpcon_dev; } modem_clock_hal_context_t; -#if !SOC_IS(ESP32H2) //TODO: PM-92 +#if SOC_PM_SUPPORT_PMU_MODEM_STATE void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain); #endif diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index b900e928a9..98eca2237f 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -27,11 +27,12 @@ menu "Example Configuration" config EXAMPLE_EXT1_WAKEUP_PIN_1 int "Enable wakeup from PIN_1" depends on !IDF_TARGET_ESP32 - default 2 if !IDF_TARGET_ESP32H2 - default 10 if IDF_TARGET_ESP32H2 + default 2 if !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32H21 + default 10 if IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32H21 range 0 7 if IDF_TARGET_ESP32C6 range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5 range 7 14 if IDF_TARGET_ESP32H2 + range 5 11 if IDF_TARGET_ESP32H21 range 0 21 if IDF_TARGET_ESP32S2 range 0 21 if IDF_TARGET_ESP32S3 range 0 15 if IDF_TARGET_ESP32P4 @@ -103,11 +104,12 @@ menu "Example Configuration" config EXAMPLE_EXT1_WAKEUP_PIN_2 int "Enable wakeup from PIN_2" depends on !IDF_TARGET_ESP32 - default 4 if !IDF_TARGET_ESP32H2 - default 11 if IDF_TARGET_ESP32H2 + default 4 if !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32H21 + default 11 if IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32H2 range 0 7 if IDF_TARGET_ESP32C6 range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5 range 7 14 if IDF_TARGET_ESP32H2 + range 5 11 if IDF_TARGET_ESP32H21 range 0 21 if IDF_TARGET_ESP32S2 range 0 21 if IDF_TARGET_ESP32S3 range 0 15 if IDF_TARGET_ESP32P4 diff --git a/examples/system/deep_sleep/main/ext_wakeup.c b/examples/system/deep_sleep/main/ext_wakeup.c index 35dcaf4b94..d0e44374ae 100644 --- a/examples/system/deep_sleep/main/ext_wakeup.c +++ b/examples/system/deep_sleep/main/ext_wakeup.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -8,7 +8,7 @@ #include "esp_sleep.h" #include "sdkconfig.h" #include "driver/rtc_io.h" - +#include "driver/gpio.h" #if CONFIG_EXAMPLE_EXT0_WAKEUP #if CONFIG_IDF_TARGET_ESP32 @@ -48,7 +48,7 @@ void example_deep_sleep_register_ext1_wakeup(void) /* If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO * during deepsleep. However, RTC IO relies on the RTC_PERIPH power domain. Keeping this power domain on will - * increase some power comsumption. However, if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH + * increase some power consumption. However, if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH * domain, we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep.*/ #if CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED diff --git a/examples/system/light_sleep/main/gpio_wakeup.c b/examples/system/light_sleep/main/gpio_wakeup.c index 7627a39926..75778640b8 100644 --- a/examples/system/light_sleep/main/gpio_wakeup.c +++ b/examples/system/light_sleep/main/gpio_wakeup.c @@ -19,6 +19,8 @@ #define BOOT_BUTTON_NUM 28 #elif CONFIG_IDF_TARGET_ESP32P4 #define BOOT_BUTTON_NUM 35 +#elif CONFIG_IDF_TARGET_ESP32H21 +#define BOOT_BUTTON_NUM 14 #else #define BOOT_BUTTON_NUM 0 #endif