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Updates for riscv support

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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
This commit is contained in:
Angus Gratton
2020-11-06 15:00:07 +11:00
parent 87e13baaf1
commit 420aef1ffe
75 changed files with 498 additions and 183 deletions
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2
components/app_trace/app_trace.c
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@@ -161,8 +161,10 @@
#if CONFIG_IDF_TARGET_ESP32S2
#include "soc/sensitive_reg.h"
#endif
#if __XTENSA__
#include "eri.h"
#include "trax.h"
#endif
#include "soc/timer_periph.h"
#include "freertos/FreeRTOS.h"
#include "esp_app_trace.h"