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Updates for riscv support

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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
This commit is contained in:
Angus Gratton
2020-11-06 15:00:07 +11:00
parent 87e13baaf1
commit 420aef1ffe
75 changed files with 498 additions and 183 deletions
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22
components/bootloader_support/src/bootloader_mem.c
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@@ -14,35 +14,17 @@
#include <stdbool.h>
#include "xtensa/config/core.h"
#include "hal/cpu_hal.h"
#include "hal/mpu_hal.h"
#include "hal/mpu_types.h"
#include "soc/soc_caps.h"
#include "bootloader_mem.h"
#include "xt_instr_macros.h"
#include "xtensa/config/specreg.h"
static inline void cpu_configure_region_protection(void)
{
/* Currently, the only supported chips esp32 and esp32s2
* have the same configuration. Move this to the port layer once
* more chips with different configurations are supported.
*
* Both chips have the address space divided into 8 regions, 512MB each.
*/
const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
for (int i = 0; i < sizeof(illegal_regions) / sizeof(illegal_regions[0]); ++i) {
mpu_hal_set_region_access(illegal_regions[i], MPU_REGION_ILLEGAL);
}
mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
}
#include "soc/cpu.h"
void bootloader_init_mem(void)
{
cpu_hal_init_hwloop();
// protect memory region
cpu_configure_region_protection();
esp_cpu_configure_region_protection();
}