Updates for riscv support

* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
This commit is contained in:
Angus Gratton
2020-11-06 15:00:07 +11:00
parent 87e13baaf1
commit 420aef1ffe
75 changed files with 498 additions and 183 deletions

View File

@@ -13,7 +13,7 @@
// limitations under the License.
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/cpu.h"
#include "hal/cpu_hal.h"
#include "soc/wdev_reg.h"
#ifndef BOOTLOADER_BUILD
@@ -44,13 +44,14 @@
values.
*/
random = REG_READ(WDEV_RND_REG);
RSR(CCOUNT, start);
start = cpu_hal_get_cycle_count();
do {
random ^= REG_READ(WDEV_RND_REG);
RSR(CCOUNT, now);
now = cpu_hal_get_cycle_count();
} while (now - start < 80 * 32 * 2); /* extra factor of 2 is precautionary */
}
buffer_bytes[i] = random >> ((i % 4) * 8);
}
}
#endif // BOOTLOADER_BUILD