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Updates for riscv support

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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
This commit is contained in:
Angus Gratton
2020-11-06 15:00:07 +11:00
parent 87e13baaf1
commit 420aef1ffe
75 changed files with 498 additions and 183 deletions
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4
components/esp32s3/CMakeLists.txt
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@@ -7,7 +7,7 @@ endif()
if(BOOTLOADER_BUILD)
# For bootloader, all we need from esp32s3 is headers
idf_component_register(INCLUDE_DIRS include)
idf_component_register(INCLUDE_DIRS include REQUIRES xtensa)
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s3.peripherals.ld")
else()
# Regular app build
@@ -25,7 +25,7 @@ else()
"system_api_esp32s3.c")
set(include_dirs "include")
set(requires driver efuse soc) #unfortunately rom/uart uses SOC registers directly
set(requires driver efuse soc xtensa) #unfortunately rom/uart uses SOC registers directly
# driver is a public requirement because esp_sleep.h uses gpio_num_t & touch_pad_t
# app_update is added here because cpu_start.c uses esp_ota_get_app_description() function.