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Updates for riscv support

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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
This commit is contained in:
Angus Gratton
2020-11-06 15:00:07 +11:00
parent 87e13baaf1
commit 420aef1ffe
75 changed files with 498 additions and 183 deletions
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2
components/esp_common/include/esp_err.h
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@@ -21,7 +21,7 @@
extern "C" {
#endif
typedef int32_t esp_err_t;
typedef int esp_err_t;
/* Definitions for error constants. */
#define ESP_OK 0 /*!< esp_err_t value indicating success (no error) */