Updates for riscv support

* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc

components/esp_gdbstub/esp32/gdbstub_esp32.c

@@ -42,7 +42,7 @@ void esp_gdbstub_putchar(int c)
 int esp_gdbstub_readmem(intptr_t addr)
 {
     if (addr < 0x20000000 || addr >= 0x80000000) {
-        /* see cpu_configure_region_protection */
+        /* see esp_cpu_configure_region_protection */
         return -1;
     }
     uint32_t val_aligned = *(uint32_t *)(addr & (~3));