Updates for riscv support

* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc

tools/find_build_apps/common.py

@@ -264,6 +264,7 @@ class BuildItem(object):
             sys.executable,
             IDF_SIZE_PY,
             '--json',
+            '--target', self.target,
             '-o', size_json_fp,
             map_file
         ]