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feat(ulp-riscv): Added new example to demonstrate ULP RISC-V interrupts

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This commit adds a new example which demonstrates how the ULP RISC-V
co-processor handles interrupts.
This commit is contained in:
Sudeep Mohanty
2023-12-14 16:15:06 +01:00
parent 94e2516f6c
commit 4230acb971
9 changed files with 293 additions and 0 deletions
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9
examples/system/ulp/ulp_riscv/interrupts/sdkconfig.defaults Normal file
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# Enable ULP
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_TYPE_RISCV=y
CONFIG_ULP_COPROC_RESERVE_MEM=4096
# Set log level to Warning to produce clean output
CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
CONFIG_BOOTLOADER_LOG_LEVEL=2
CONFIG_LOG_DEFAULT_LEVEL_WARN=y
CONFIG_LOG_DEFAULT_LEVEL=2