alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-28 21:33:32 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix(mspi): fixed mspi clock wrong on ram loadable app on c5

Browse Source
This commit is contained in:
Armando
2024-09-08 10:03:45 +08:00
parent f0a2091e4d
commit 42cf1d8867
4 changed files with 16 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
View File

@@ -48,8 +48,18 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
bootloader_init_mspi_clock();
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -204,11 +214,7 @@ static void bootloader_spi_flash_resume(void)
esp_err_t bootloader_init_spi_flash(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
bootloader_init_mspi_clock();
bootloader_init_flash_configure();
bootloader_spi_flash_resume();

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
View File

@@ -42,7 +42,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_flash_init_core_clock(void)
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
_spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
_spimem_ctrlr_ll_set_core_clock(0, 6);
@@ -50,7 +50,7 @@ void IRAM_ATTR bootloader_flash_init_core_clock(void)
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
bootloader_flash_init_core_clock();
bootloader_init_mspi_clock();
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {