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Merge branch 'master' into feature/esp32s2beta_merge

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Angus Gratton
2019-09-16 10:56:48 +10:00
committed by Angus Gratton
parent 0efdeb202e c27fd32fbe
commit 438d513a95
361 changed files with 10271 additions and 7062 deletions
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4
docs/en/api-guides/fatal-errors.rst
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@@ -62,6 +62,10 @@ Behavior of panic handler is affected by two other configuration options.
- If :doc:`Core Dump <core_dump>` feature is enabled (``CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH`` or ``CONFIG_ESP32_ENABLE_COREDUMP_TO_UART`` options), then system state (task stacks and registers) will be dumped either to Flash or UART, for later analysis.
- If :ref:`CONFIG_ESP_PANIC_HANDLER_IRAM` is disabled (disabled by default), the panic handler code is placed in flash memory not IRAM. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor risk, if the flash cache status is also corrupted during the crash.
If this option is enabled, the panic handler code is placed in IRAM. This allows the panic handler to run without needing to re-enable cache first. This may be necessary to debug some complex issues with crashes while flash cache is disabled (for example, when writing to SPI flash).
The following diagram illustrates panic handler behavior:
.. blockdiag::