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spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2

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This commit is contained in:
Cao Sen Miao
2022-04-12 16:37:40 +08:00
parent 68d4c47b7e
commit 4418a855ba
57 changed files with 871 additions and 547 deletions
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16
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@@ -487,6 +487,22 @@ config SOC_SPI_MAX_PRE_DIVIDER
int
default 8192
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_TIMER_GROUPS
int
default 2

5
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -262,6 +262,11 @@
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_MAX_PRE_DIVIDER 8192
// Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
// Peripheral supports DIO, DOUT, QIO, or QOUT