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Merge branch 'refactor/common_rom_uart_apis' into 'master'

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esp_rom: extract common uart apis into esp_rom_uart.h

See merge request espressif/esp-idf!9313
This commit is contained in:
Angus Gratton
2020-07-21 15:24:21 +08:00
parent 3755fb6597 345606e7f3
commit 442736c5d6
44 changed files with 274 additions and 150 deletions
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5
components/bootloader_support/src/bootloader_clock.c
View File

@@ -19,14 +19,13 @@
#include "soc/rtc_cntl_reg.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#include "esp32/rom/rtc.h"
#define CPU_RESET_REASON SW_CPU_RESET
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/rtc.h"
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#endif
#include "esp_rom_uart.h"
void bootloader_clock_configure(void)
{
@@ -35,7 +34,7 @@ void bootloader_clock_configure(void)
// This is not needed on power on reset, when ROM bootloader is running at
// 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
// and will be done with the bootloader much earlier than UART FIFO is empty.
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
/* Set CPU to 80MHz. Keep other clocks unmodified. */
int cpu_freq_mhz = 80;

16
components/bootloader_support/src/bootloader_console.c
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@@ -23,14 +23,13 @@
#include "hal/clk_gate_ll.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_common.h"
#endif
#include "esp_rom_gpio.h"
#include "esp_rom_uart.h"
#ifdef CONFIG_ESP_CONSOLE_UART_NONE
void bootloader_console_init(void)
@@ -48,7 +47,7 @@ void bootloader_console_init(void)
ets_install_uart_printf();
// Wait for UART FIFO to be empty.
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
// Some constants to make the following code less upper-case
@@ -56,7 +55,7 @@ void bootloader_console_init(void)
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
// Switch to the new UART (this just changes UART number used for
// ets_printf in ROM code).
uart_tx_switch(uart_num);
esp_rom_uart_set_as_console(uart_num);
// If console is attached to UART1 or if non-default pins are used,
// need to reconfigure pins using GPIO matrix
if (uart_num != 0 ||
@@ -78,14 +77,13 @@ void bootloader_console_init(void)
#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
// Set configured UART console baud rate
const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
esp_rom_uart_set_clock_baudrate(uart_num, rtc_clk_apb_freq_get(), CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}
#endif // CONFIG_ESP_CONSOLE_UART
#ifdef CONFIG_ESP_CONSOLE_USB_CDC
/* Buffer for CDC data structures. No RX buffer allocated. */
static char s_usb_cdc_buf[CDC_ACM_WORK_BUF_MIN];
static char s_usb_cdc_buf[ESP_ROM_CDC_ACM_WORK_BUF_MIN];
void bootloader_console_init(void)
{
@@ -96,8 +94,8 @@ void bootloader_console_init(void)
rom_usb_cdc_set_descriptor_patch();
#endif
Uart_Init_USB(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
uart_tx_switch(ROM_UART_USB);
esp_rom_uart_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
esp_rom_uart_set_as_console(ESP_ROM_UART_USB);
ets_install_putc1(bootloader_console_write_char_usb);
}
#endif //CONFIG_ESP_CONSOLE_USB_CDC

7
components/bootloader_support/src/bootloader_console_loader.c
View File

@@ -20,12 +20,11 @@
#include <stddef.h>
#include "sdkconfig.h"
#include "bootloader_console.h"
#include "esp_rom_uart.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
@@ -33,7 +32,7 @@
#endif
#ifdef CONFIG_ESP_CONSOLE_USB_CDC
/* The following functions replace ets_write_char_uart, uart_tx_one_char,
/* The following functions replace ets_write_char_uart, esp_rom_uart_tx_one_char,
* and uart_tx_one_char_uart ROM functions. The main difference is that
* uart_tx_one_char_uart calls cdc_acm_fifo_fill for each byte passed to it,
* which results in very slow console output. The version here uses a TX buffer.
@@ -73,7 +72,7 @@ void bootloader_console_deinit(void)
{
#ifdef CONFIG_ESP_CONSOLE_UART
/* Ensure any buffered log output is displayed */
uart_tx_flush(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_flush_tx(CONFIG_ESP_CONSOLE_UART_NUM);
#endif // CONFIG_ESP_CONSOLE_UART
#ifdef CONFIG_ESP_CONSOLE_USB_CDC

5
components/bootloader_support/src/bootloader_utility.c
View File

@@ -24,20 +24,19 @@
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#else
#error "Unsupported IDF_TARGET"
#endif
#include "esp_rom_uart.h"
#include "soc/soc.h"
#include "soc/cpu.h"
@@ -612,7 +611,7 @@ static void load_image(const esp_image_metadata_t *image_data)
so issue a system reset to ensure flash encryption
cache resets properly */
ESP_LOGI(TAG, "Resetting with flash encryption enabled...");
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
bootloader_reset();
}
#endif

1
components/bootloader_support/src/esp32/bootloader_esp32.c
View File

@@ -40,7 +40,6 @@
#include "esp_rom_efuse.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
static const char *TAG = "boot.esp32";