Merge branch 'feature/efuse_hal' into 'master'

hal: Adds efuse hal layer

See merge request espressif/esp-idf!16354

components/hal/esp32c2/efuse_hal.c

@@ -0,0 +1,63 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include <sys/param.h>
+#include "soc/soc_caps.h"
+#include "hal/assert.h"
+#include "hal/efuse_hal.h"
+#include "hal/efuse_ll.h"
+
+
+uint32_t efuse_hal_get_chip_revision(void)
+{
+    return efuse_ll_get_chip_revision();
+}
+
+/******************* eFuse control functions *************************/
+
+void efuse_hal_set_timing(uint32_t apb_freq_hz)
+{
+    (void) apb_freq_hz;
+    efuse_ll_set_pwr_off_num(0x190);
+}
+
+void efuse_hal_read(void)
+{
+    efuse_hal_set_timing(0);
+
+    efuse_ll_set_conf_read_op_code();
+    efuse_ll_set_read_cmd();
+
+    while (efuse_ll_get_read_cmd() != 0) { }
+    /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
+    while (efuse_ll_get_read_cmd() != 0) { }
+}
+
+void efuse_hal_clear_program_registers(void)
+{
+    ets_efuse_clear_program_registers();
+}
+
+void efuse_hal_program(uint32_t block)
+{
+    efuse_hal_set_timing(0);
+
+    efuse_ll_set_conf_write_op_code();
+    efuse_ll_set_pgm_cmd(block);
+
+    while (efuse_ll_get_pgm_cmd() != 0) { }
+
+    efuse_hal_clear_program_registers();
+    efuse_hal_read();
+}
+
+void efuse_hal_rs_calculate(const void *data, void *rs_values)
+{
+    ets_efuse_rs_calculate(data, rs_values);
+}
+
+/******************* eFuse control functions *************************/

components/hal/esp32c2/include/hal/efuse_hal.h

@@ -0,0 +1,59 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include_next "hal/efuse_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief get chip version
+ */
+uint32_t efuse_hal_get_chip_revision(void);
+
+/**
+ * @brief set eFuse timings
+ *
+ * @param apb_freq_hz APB frequency in Hz
+ */
+void efuse_hal_set_timing(uint32_t apb_freq_hz);
+
+/**
+ * @brief trigger eFuse read operation
+ */
+void efuse_hal_read(void);
+
+/**
+ * @brief clear registers for programming eFuses
+ */
+void efuse_hal_clear_program_registers(void);
+
+/**
+ * @brief burn eFuses written in programming registers (one block at once)
+ *
+ * @param block block number
+ */
+void efuse_hal_program(uint32_t block);
+
+/**
+ * @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
+ *
+ * @param data Pointer to data buffer (length 32 bytes)
+ * @param rs_values Pointer to write encoded data to (length 12 bytes)
+ */
+void efuse_hal_rs_calculate(const void *data, void *rs_values);
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c2/include/hal/efuse_ll.h

@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/efuse_periph.h"
+#include "hal/assert.h"
+#include "esp32c2/rom/efuse.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Always inline these functions even no gcc optimization is applied.
+
+/******************* eFuse fields *************************/
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
+{
+    return EFUSE.rd_repeat_data0.spi_boot_encrypt_decrypt_cnt;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
+{
+    return EFUSE.rd_repeat_data0.wdt_delay_sel;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
+{
+    return EFUSE.rd_blk2_data0.blk2_data0;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
+{
+    return EFUSE.rd_blk2_data1.mac_id_high;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
+{
+    return EFUSE.rd_repeat_data0.secure_boot_en;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void)
+{
+    return EFUSE.rd_blk2_data1.wafer_version;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
+{
+    return EFUSE.rd_blk2_data1.pkg_version;
+}
+
+/******************* eFuse control functions *************************/
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
+{
+    return EFUSE.cmd.read_cmd;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
+{
+    return EFUSE.cmd.pgm_cmd;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
+{
+    EFUSE.cmd.read_cmd = 1;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
+{
+    HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
+    EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
+{
+    EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
+{
+    EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
+{
+    EFUSE.wr_tim_conf2.pwr_off_num = value;
+}
+
+/******************* eFuse control functions *************************/
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c2/include/hal/rwdt_ll.h

@@ -17,7 +17,7 @@ extern "C" {
 #include <stdbool.h>
 #include "hal/wdt_types.h"
 #include "soc/rtc_cntl_periph.h"
-#include "soc/efuse_reg.h"
+#include "hal/efuse_ll.h"
 #include "esp_attr.h"
 
 //Type check wdt_stage_action_t
@@ -94,7 +94,7 @@ FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stag
     case WDT_STAGE0:
         hw->wdt_config0.stg0 = behavior;
         //Account of implicty multiplier applied to stage 0 timeout tick config value
-        hw->wdt_config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG, EFUSE_WDT_DELAY_SEL));
+        hw->wdt_config1 = timeout_ticks >> (1 + efuse_ll_get_wdt_delay_sel());
         break;
     case WDT_STAGE1:
         hw->wdt_config0.stg1 = behavior;