Merge branch 'feature/efuse_hal' into 'master'

hal: Adds efuse hal layer

See merge request espressif/esp-idf!16354
This commit is contained in:
Konstantin Kondrashov
2022-02-28 13:38:43 +08:00
87 changed files with 2011 additions and 692 deletions

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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -216,12 +216,11 @@
#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
/* Deprecated */
#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/
#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/
#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/
#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/
/* EFUSE_RD_CHIP_VER_REV2 : RO ;bitpos:[20] ;default: 8'b0 ; */
#define EFUSE_RD_CHIP_VER_REV2 0x00000001
#define EFUSE_RD_CHIP_VER_REV2_M ((EFUSE_RD_CHIP_VER_REV2_V)<<(EFUSE_RD_CHIP_VER_REV2_S))
#define EFUSE_RD_CHIP_VER_REV2_V 0x1
#define EFUSE_RD_CHIP_VER_REV2_S 20
/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_cs0*/
#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F
@@ -1054,6 +1053,9 @@
#define EFUSE_CLK_SEL0_V 0xFF
#define EFUSE_CLK_SEL0_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc)
/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: */

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@@ -0,0 +1,106 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct efuse_dev_s {
uint32_t blk0_rdata0;
uint32_t blk0_rdata1;
uint32_t blk0_rdata2;
uint32_t blk0_rdata3;
uint32_t blk0_rdata4;
uint32_t blk0_rdata5;
uint32_t blk0_rdata6;
uint32_t blk0_wdata0;
uint32_t blk0_wdata1;
uint32_t blk0_wdata2;
uint32_t blk0_wdata3;
uint32_t blk0_wdata4;
uint32_t blk0_wdata5;
uint32_t blk0_wdata6;
uint32_t blk1_rdata0;
uint32_t blk1_rdata1;
uint32_t blk1_rdata2;
uint32_t blk1_rdata3;
uint32_t blk1_rdata4;
uint32_t blk1_rdata5;
uint32_t blk1_rdata6;
uint32_t blk1_rdata7;
uint32_t blk2_rdata0;
uint32_t blk2_rdata1;
uint32_t blk2_rdata2;
uint32_t blk2_rdata3;
uint32_t blk2_rdata4;
uint32_t blk2_rdata5;
uint32_t blk2_rdata6;
uint32_t blk2_rdata7;
uint32_t blk3_rdata0;
uint32_t blk3_rdata1;
uint32_t blk3_rdata2;
uint32_t blk3_rdata3;
uint32_t blk3_rdata4;
uint32_t blk3_rdata5;
uint32_t blk3_rdata6;
uint32_t blk3_rdata7;
uint32_t blk1_wdata0;
uint32_t blk1_wdata1;
uint32_t blk1_wdata2;
uint32_t blk1_wdata3;
uint32_t blk1_wdata4;
uint32_t blk1_wdata5;
uint32_t blk1_wdata6;
uint32_t blk1_wdata7;
uint32_t blk2_wdata0;
uint32_t blk2_wdata1;
uint32_t blk2_wdata2;
uint32_t blk2_wdata3;
uint32_t blk2_wdata4;
uint32_t blk2_wdata5;
uint32_t blk2_wdata6;
uint32_t blk2_wdata7;
uint32_t blk3_wdata0;
uint32_t blk3_wdata1;
uint32_t blk3_wdata2;
uint32_t blk3_wdata3;
uint32_t blk3_wdata4;
uint32_t blk3_wdata5;
uint32_t blk3_wdata6;
uint32_t blk3_wdata7;
uint32_t clk;
uint32_t conf;
uint32_t status;
uint32_t cmd;
uint32_t int_raw;
uint32_t int_st;
uint32_t int_ena;
uint32_t int_clr;
uint32_t dac_conf;
uint32_t dec_status;
uint32_t reserve[55];
uint32_t date;
} efuse_dev_t;
extern efuse_dev_t EFUSE;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_EFUSE_STRUCT_H_ */