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https://github.com/espressif/esp-idf.git
synced 2025-09-30 19:19:21 +00:00
feat(dsi): add mipi dsi hal+ll layer driver
This commit is contained in:
morris
@@ -23,11 +23,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
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switch (periph) {
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case PERIPH_EMAC_MODULE:
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return LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN | LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN | LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN;
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case PERIPH_MIPI_DSI_MODULE:
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return HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN;
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// IDF-6500
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case PERIPH_MIPI_CSI_MODULE:
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return 0;
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case PERIPH_I3C_MODULE:
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return HP_SYS_CLKRST_REG_I3C_MST_CLK_EN;
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case PERIPH_SARADC_MODULE:
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@@ -63,10 +58,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
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switch (periph) {
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case PERIPH_PVT_MODULE:
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return HP_SYS_CLKRST_REG_RST_EN_PVT_TOP;
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case PERIPH_MIPI_DSI_MODULE:
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return HP_SYS_CLKRST_REG_RST_EN_DSI_BRG;
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case PERIPH_MIPI_CSI_MODULE:
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return HP_SYS_CLKRST_REG_RST_EN_CSI_BRG;
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case PERIPH_ISP_MODULE:
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return HP_SYS_CLKRST_REG_RST_EN_ISP;
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case PERIPH_DMA2D_MODULE:
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@@ -124,8 +115,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
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static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
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{
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switch (periph) {
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case PERIPH_MIPI_DSI_MODULE:
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return HP_SYS_CLKRST_PERI_CLK_CTRL03_REG;
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case PERIPH_I3C_MODULE:
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case PERIPH_SARADC_MODULE:
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return HP_SYS_CLKRST_PERI_CLK_CTRL22_REG;
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@@ -42,9 +42,10 @@ typedef enum {
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} lcd_ll_swizzle_mode_t;
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/**
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* @brief Enable or disable the bus clock for the LCD module
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* @brief Enable the bus clock for LCD module
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*
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* @param set_bit True to set bit, false to clear bit
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* @param group_id Group ID
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* @param enable true to enable, false to disable
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*/
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static inline void lcd_ll_enable_bus_clock(int group_id, bool enable)
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{
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@@ -58,6 +59,8 @@ static inline void lcd_ll_enable_bus_clock(int group_id, bool enable)
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/**
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* @brief Reset the LCD module
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*
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* @param group_id Group ID
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*/
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static inline void lcd_ll_reset_register(int group_id)
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{
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270
components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h
Normal file
270
components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h
Normal file
@@ -0,0 +1,270 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "hal/assert.h"
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#include "soc/mipi_dsi_bridge_struct.h"
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#include "hal/mipi_dsi_types.h"
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#include "hal/lcd_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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MIPI_DSI_LL_FLOW_CONTROLLER_DMA, ///< DMA controller as the flow controller
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MIPI_DSI_LL_FLOW_CONTROLLER_BRIDGE, ///< DSI bridge is the flow controller
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} mipi_dsi_ll_flow_controller_t;
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/**
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* @brief Enable the DSI bridge
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param en True to enable, false to disable
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*/
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static inline void mipi_dsi_brg_ll_enable(dsi_brg_dev_t *dev, bool en)
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{
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dev->en.dsi_en = en;
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}
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/**
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* @brief Set the number of 64-bit words in one dma burst transfer
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*
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* @note valid only when dsi_bridge is the flow controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param burst_len Number of 64-bit words in one dma burst transfer
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*/
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static inline void mipi_dsi_brg_ll_set_burst_len(dsi_brg_dev_t *dev, uint32_t burst_len)
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{
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dev->dma_req_cfg.dma_burst_len = burst_len;
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}
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/**
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* @brief Set the number of pixel bits in total
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*
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* @note valid only when dsi_bridge is the flow controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param num_pixel_bits Number of pixel bits, must be aligned to 64
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*/
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static inline void mipi_dsi_brg_ll_set_num_pixel_bits(dsi_brg_dev_t *dev, uint32_t num_pixel_bits)
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{
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dev->raw_num_cfg.raw_num_total = num_pixel_bits / 64;
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// reload the value into internal counter
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dev->raw_num_cfg.raw_num_total_set = 1;
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}
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/**
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* @brief Set the threshold whether the dsi_bridge FIFO can receive one more 64-bit
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*
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* @note valid only when dsi_bridge is the flow controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param threshold Threshold value
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*/
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static inline void mipi_dsi_brg_ll_credit_set_threshold(dsi_brg_dev_t *dev, uint32_t threshold)
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{
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dev->raw_buf_credit_ctl.credit_thrd = threshold;
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}
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/**
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* @brief Set the threshold whether the dsi_bridge FIFO can receive one more DMA burst
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*
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* @note valid only when dsi_bridge is the flow controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param threshold Threshold value
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*/
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static inline void mipi_dsi_brg_ll_credit_set_burst_threshold(dsi_brg_dev_t *dev, uint32_t threshold)
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{
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dev->raw_buf_credit_ctl.credit_burst_thrd = threshold;
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}
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/**
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* @brief Reset the credit counter of the DSI bridge
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*
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* @note valid only when dsi_bridge is the flow controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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*/
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static inline void mipi_dsi_brg_ll_credit_reset(dsi_brg_dev_t *dev)
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{
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dev->raw_buf_credit_ctl.credit_reset = 1;
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}
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/**
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* @brief Set the color coding for the bridge controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param pixel_format Color coding
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* @param sub_config Sub configuration
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*/
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static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_rgb_pixel_format_t pixel_format, uint32_t sub_config)
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{
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switch (pixel_format) {
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case LCD_COLOR_PIXEL_FORMAT_RGB565:
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dev->pixel_type.raw_type = 2;
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break;
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case LCD_COLOR_PIXEL_FORMAT_RGB666:
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dev->pixel_type.raw_type = 1;
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break;
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case LCD_COLOR_PIXEL_FORMAT_RGB888:
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dev->pixel_type.raw_type = 0;
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break;
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default:
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abort();
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}
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dev->pixel_type.dpi_config = sub_config;
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}
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/**
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* @brief Set the color space for input color data
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param color_space Color space type
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*/
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static inline void mipi_dsi_brg_ll_set_input_color_space(dsi_brg_dev_t *dev, lcd_color_space_t color_space)
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{
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switch (color_space) {
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case LCD_COLOR_SPACE_RGB:
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dev->pixel_type.data_in_type = 0;
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break;
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case LCD_COLOR_SPACE_YUV:
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dev->pixel_type.data_in_type = 1;
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break;
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default:
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abort();
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}
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}
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/**
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* @brief Set the vertical timing parameters for the bridge controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param vsw Vertical sync width
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* @param vbp Vertical back porch
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* @param active_height Active height
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* @param vfp Vertical front porch
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*/
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static inline void mipi_dsi_brg_ll_set_vertical_timing(dsi_brg_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp)
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{
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dev->dpi_v_cfg0.vdisp = active_height;
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dev->dpi_v_cfg0.vtotal = vsw + vbp + active_height + vfp;
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dev->dpi_v_cfg1.vsync = vsw;
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dev->dpi_v_cfg1.vbank = vbp;
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}
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/**
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* @brief Set the horizontal timing parameters for the bridge controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param hsw Horizontal sync width
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* @param hbp Horizontal back porch
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* @param active_width Active width
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* @param hfp Horizontal front porch
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*/
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static inline void mipi_dsi_brg_ll_set_horizontal_timing(dsi_brg_dev_t *dev, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp)
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{
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dev->dpi_h_cfg0.hdisp = active_width;
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dev->dpi_h_cfg0.htotal = hsw + hbp + active_width + hfp;
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dev->dpi_h_cfg1.hsync = hsw;
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dev->dpi_h_cfg1.hbank = hbp;
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}
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/**
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* @brief Set the under run discard count for the bridge controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param under_run_discard_count Under run discard count
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*/
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static inline void mipi_dsi_brg_ll_set_underrun_discard_count(dsi_brg_dev_t *dev, uint32_t under_run_discard_count)
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{
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dev->dpi_misc_config.fifo_underrun_discard_vcnt = under_run_discard_count;
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}
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/**
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* @brief Enable the DPI output
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param en True to enable, false to disable
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*/
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static inline void mipi_dsi_brg_ll_enable_dpi_output(dsi_brg_dev_t *dev, bool en)
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{
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dev->dpi_misc_config.dpi_en = en;
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}
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/**
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* @brief Update the configuration of DSI bridge
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*
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* @param dev Pointer to the DSI bridge controller register base address
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*/
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static inline void mipi_dsi_brg_ll_update_config(dsi_brg_dev_t *dev)
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{
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dev->dpi_config_update.dpi_config_update = 1;
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}
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/**
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* @brief Enable the refclk and cfg_clk of dsi host
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param en True to enable, false to disable
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*/
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static inline void mipi_dsi_brg_ll_enable_ref_clock(dsi_brg_dev_t *dev, bool en)
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{
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dev->host_ctrl.dsi_cfg_ref_clk_en = en;
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}
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/**
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* @brief Set the flow controller of DMA transfer
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param controller Flow controller
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*/
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static inline void mipi_dsi_brg_ll_set_flow_controller(dsi_brg_dev_t* dev, mipi_dsi_ll_flow_controller_t controller)
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{
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dev->dma_flow_ctrl.dsi_dma_flow_controller = controller;
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}
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/**
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* @brief Set the number of blocks when multi-block transfer is enabled
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*
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* @note only valid when DMAC is the flow controller
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param number Number of blocks
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*/
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static inline void mipi_dsi_brg_ll_set_multi_block_number(dsi_brg_dev_t* dev, uint32_t number)
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{
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dev->dma_flow_ctrl.dma_flow_multiblk_num = number;
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}
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/**
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* @brief Set the YUV-RGB conversion standard
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*
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* @param dev Pointer to the DSI bridge controller register base address
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* @param std YUV-RGB conversion standard
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*/
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static inline void mipi_dsi_brg_ll_set_yuv_convert_std(dsi_brg_dev_t* dev, lcd_yuv_conv_std_t std)
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{
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switch (std) {
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case LCD_YUV_CONV_STD_BT601:
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dev->yuv_cfg.protocal = 0;
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break;
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case LCD_YUV_CONV_STD_BT709:
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dev->yuv_cfg.protocal = 1;
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break;
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default:
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abort();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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769
components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h
Normal file
769
components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h
Normal file
@@ -0,0 +1,769 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "soc/mipi_dsi_host_struct.h"
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#include "hal/mipi_dsi_types.h"
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#include "hal/lcd_types.h"
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#define MIPI_DSI_LL_MAX_DPI_CLK_DIV 256
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief MIPI DSI transmission speed mode
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*/
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typedef enum {
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MIPI_DSI_LL_TRANS_SPEED_HS, /*!< High speed transmission */
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MIPI_DSI_LL_TRANS_SPEED_LP, /*!< Low power transmission */
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} mipi_dsi_ll_trans_speed_mode_t;
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/**
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* @brief Color coding type (depth and pixel configuration)
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*/
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typedef enum {
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MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG1 = 0, // 16-bit configuration 1
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MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG2 = 1, // 16-bit configuration 2
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MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG3 = 2, // 16-bit configuration 3
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MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG1 = 3, // 18-bit configuration 1
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MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG2 = 4, // 18-bit configuration 2
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MIPI_DSI_LL_COLOR_CODE_24BIT = 5, // 24-bit
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} mipi_dsi_ll_color_coding_t;
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/**
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* @brief The kind of test pattern that can be generated by the DSI Host controller
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*/
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typedef enum {
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MIPI_DSI_LL_PATTERN_BAR_VERTICAL, // Vertical bar pattern
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MIPI_DSI_LL_PATTERN_BAR_HORIZONTAL, // Horizontal bar pattern
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MIPI_DSI_LL_PATTERN_BER_VERTICAL, // Vertical ber pattern
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} mipi_dsi_ll_pattern_type_t;
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/**
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* @brief MIPI DSI Video mode burst type
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*/
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typedef enum {
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MIPI_DSI_LL_VIDEO_NON_BURST_WITH_SYNC_PULSES, // Non-burst mode with sync pulses
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MIPI_DSI_LL_VIDEO_NON_BURST_WITH_SYNC_EVENTS, // Non-burst mode with sync events
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MIPI_DSI_LL_VIDEO_BURST_WITH_SYNC_PULSES, // Burst mode with sync pulses
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} mipi_dsi_ll_video_burst_type_t;
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/**
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* @brief Set the DSI Host controller power state
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*
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* @param dev Pointer to the DSI Host controller register base address
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||||
* @param True to turn on, False to turn off
|
||||
*/
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static inline void mipi_dsi_host_ll_power_on_off(dsi_host_dev_t *dev, bool on)
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{
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dev->pwr_up.shutdownz = on;
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}
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||||
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/**
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* @brief Set the division factor for the Time Out clock
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*
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* @note The Time Out clock is the clock used as the timing unit in the configuration of HS->LP and LP->HS transition error.
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||||
* @note Time out clock source is lane byte clock
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||||
*
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* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param div Division factor for the Time Out clock
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||||
*/
|
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static inline void mipi_dsi_host_ll_set_timeout_clock_division(dsi_host_dev_t *dev, uint32_t div)
|
||||
{
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||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->clkmgr_cfg, to_clk_division, div - 1);
|
||||
}
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||||
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||||
/**
|
||||
* @brief Set the division factor for the Escape clock
|
||||
*
|
||||
* @note TX Escape clock source is lane byte clock
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param div Division factor for the Escape clock
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_escape_clock_division(dsi_host_dev_t *dev, uint32_t div)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->clkmgr_cfg, tx_esc_clk_division, div - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the timeout counts for various operations
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param hs_tx Timeout count for HS transmission, measured in TO_CLK_DIVISION cycles
|
||||
* @param lp_rx Timeout count for LP reception, measured in TO_CLK_DIVISION cycles
|
||||
* @param hs_rd Timeout count for HS read, measured in lane byte clock cycles
|
||||
* @param lp_rd Timeout count for LP read, measured in lane byte clock cycles
|
||||
* @param hs_wr Timeout count for HS write, measured in lane byte clock cycles
|
||||
* @param lp_wr Timeout count for LP write, measured in lane byte clock cycles
|
||||
* @param bta Timeout count for BTA, measured in lane byte clock cycles
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_timeout_count(dsi_host_dev_t *dev, uint32_t hs_tx, uint32_t lp_rx, uint32_t hs_rd, uint32_t lp_rd, uint32_t hs_wr, uint32_t lp_wr, uint32_t bta)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, hstx_to_cnt, hs_tx);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, lprx_to_cnt, lp_rx);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_rd_to_cnt, hs_rd_to_cnt, hs_rd);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_rd_to_cnt, lp_rd_to_cnt, lp_rd);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_wr_to_cnt, hs_wr_to_cnt, hs_wr);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_wr_to_cnt, lp_wr_to_cnt, lp_wr);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->bta_to_cnt, bta_to_cnt, bta);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the automatic mechanism to stop providing clock in the clock lane when time allows
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_non_continuous_clock(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->lpclk_ctrl.auto_clklane_ctrl = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Request the PHY module to start transmission of high speed clock
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_hs_clock(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->lpclk_ctrl.phy_txrequestclkhs = enable;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////DPI Interface///////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set DPI virtual channel ID that will be indexed to the video mode packets
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param vcid Virtual channel ID
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_vcid(dsi_host_dev_t *dev, uint32_t vcid)
|
||||
{
|
||||
dev->dpi_vcid.dpi_vcid = vcid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set DPI video color coding
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param color_coding Color coding value
|
||||
* @param sub_config Sub configuration value
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_color_coding(dsi_host_dev_t *dev, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config)
|
||||
{
|
||||
switch (color_coding) {
|
||||
case LCD_COLOR_PIXEL_FORMAT_RGB565:
|
||||
dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG1 + sub_config;
|
||||
break;
|
||||
case LCD_COLOR_PIXEL_FORMAT_RGB666:
|
||||
dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG1 + sub_config;
|
||||
break;
|
||||
case LCD_COLOR_PIXEL_FORMAT_RGB888:
|
||||
dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_24BIT;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DPI loosely packetization video (used only when color depth = 18)
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_loosely18_packet(dsi_host_dev_t *dev, bool en)
|
||||
{
|
||||
dev->dpi_color_coding.loosely18_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set DPI timing signal polarity
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param hsync_active_low If the HSYNC signal is active low
|
||||
* @param vsync_active_low If the VSYNC signal is active low
|
||||
* @param de_active_low If the DE signal is active low
|
||||
* @param shut_down_active_low If the SHUTDOWNZ signal is active low
|
||||
* @param color_mode_active_low If the COLORM active low
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_timing_polarity(dsi_host_dev_t *dev, bool hsync_active_low, bool vsync_active_low, bool de_active_low, bool shut_down_active_low, bool color_mode_active_low)
|
||||
{
|
||||
dev->dpi_cfg_pol.hsync_active_low = hsync_active_low;
|
||||
dev->dpi_cfg_pol.vsync_active_low = vsync_active_low;
|
||||
dev->dpi_cfg_pol.dataen_active_low = de_active_low;
|
||||
dev->dpi_cfg_pol.shutd_active_low = shut_down_active_low;
|
||||
dev->dpi_cfg_pol.colorm_active_low = color_mode_active_low;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable frame BTA acknowledgement
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_frame_ack(dsi_host_dev_t *dev, bool en)
|
||||
{
|
||||
dev->vid_mode_cfg.frame_bta_ack_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable return to low power mode inside horizontal front/back porch periods when timing allows
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param en_hbp True to enable, False to disable
|
||||
* @param en_hfp True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_lp_horizontal_timing(dsi_host_dev_t *dev, bool en_hbp, bool en_hfp)
|
||||
{
|
||||
dev->vid_mode_cfg.lp_hbp_en = en_hbp;
|
||||
dev->vid_mode_cfg.lp_hfp_en = en_hfp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable return to low power mode inside vertical timing periods (e.g. vbp) when timing allows
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param en_vsync True to enable, False to disable
|
||||
* @param en_vbp True to enable, False to disable
|
||||
* @param en_vfp True to enable, False to disable
|
||||
* @param en_vact True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_lp_vertical_timing(dsi_host_dev_t *dev, bool en_vsync, bool en_vbp, bool en_vfp, bool en_vact)
|
||||
{
|
||||
dev->vid_mode_cfg.lp_vsa_en = en_vsync;
|
||||
dev->vid_mode_cfg.lp_vbp_en = en_vbp;
|
||||
dev->vid_mode_cfg.lp_vfp_en = en_vfp;
|
||||
dev->vid_mode_cfg.lp_vact_en = en_vact;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the command transmission in LP mode
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_lp_command(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->vid_mode_cfg.lp_cmd_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set MIPI DSI video burst type
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param mode Video mode type
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_video_burst_type(dsi_host_dev_t *dev, mipi_dsi_ll_video_burst_type_t type)
|
||||
{
|
||||
dev->vid_mode_cfg.vid_mode_type = type;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the kind of the pattern to be generated by the DSI Host controller
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param type Pattern type
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_pattern_type(dsi_host_dev_t *dev, mipi_dsi_ll_pattern_type_t type)
|
||||
{
|
||||
switch (type) {
|
||||
case MIPI_DSI_LL_PATTERN_BAR_HORIZONTAL:
|
||||
dev->vid_mode_cfg.vpg_mode = 0;
|
||||
dev->vid_mode_cfg.vpg_orientation = 1;
|
||||
break;
|
||||
case MIPI_DSI_LL_PATTERN_BAR_VERTICAL:
|
||||
dev->vid_mode_cfg.vpg_mode = 0;
|
||||
dev->vid_mode_cfg.vpg_orientation = 0;
|
||||
break;
|
||||
case MIPI_DSI_LL_PATTERN_BER_VERTICAL:
|
||||
dev->vid_mode_cfg.vpg_mode = 1;
|
||||
dev->vid_mode_cfg.vpg_orientation = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable pattern generation
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_pattern(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->vid_mode_cfg.vpg_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable / Disable DPI video mode
|
||||
*
|
||||
* @note Commands can still be sent by the generic interface while in video mode
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_enable_video_mode(dsi_host_dev_t *dev, bool en)
|
||||
{
|
||||
dev->mode_cfg.cmd_video_mode = !en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of bytes inside a null packet
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param packet_size Number of bytes inside a null packet, 0 means to disable the null packet
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_null_packet_size(dsi_host_dev_t *dev, uint32_t packet_size)
|
||||
{
|
||||
dev->vid_null_size.vid_null_size = packet_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Se the number of chunks to be transmitted during a Line period
|
||||
*
|
||||
* @note A trunk is pair of video packet and null packet
|
||||
* @note The data in each chunk is set in `mipi_dsi_host_ll_dpi_set_video_packet_pixel_num`
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param trunk_num Number of chunks. 0 - video line is transmitted in a single packet
|
||||
* 1 - video line is transmitted in a single packet, followed by a null packet
|
||||
* Others - Multiple chunks are used to transmit each video line
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_trunks_num(dsi_host_dev_t *dev, uint32_t trunks_num)
|
||||
{
|
||||
dev->vid_num_chunks.vid_num_chunks = trunks_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of pixels in a signal video packet
|
||||
*
|
||||
* @note For 18-bit not loosely packed data types, the size must be a multiple of 4
|
||||
* @note For YUV data types, the size must be a multiple of 2
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param packet_pixels Number of pixels in a signal video packet
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_video_packet_pixel_num(dsi_host_dev_t *dev, uint32_t packet_pixels)
|
||||
{
|
||||
dev->vid_pkt_size.vid_pkt_size = packet_pixels;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set vertical timing parameters of video mode
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param vsw Vertical Synchronization Width, in lines
|
||||
* @param vbp Vertical Back Porch period, in lines
|
||||
* @param active_height Vertical active height, in lines
|
||||
* @param vfp Vertical Front Porch period, in lines
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_vertical_timing(dsi_host_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp)
|
||||
{
|
||||
dev->vid_vsa_lines.vsa_lines = vsw;
|
||||
dev->vid_vbp_lines.vbp_lines = vbp;
|
||||
dev->vid_vactive_lines.v_active_lines = active_height;
|
||||
dev->vid_vfp_lines.vfp_lines = vfp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set horizontal timing parameters of video mode
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param hsw Horizontal Synchronization Width, in lane byte clock cycles
|
||||
* @param hbp Horizontal Back Porch period, in lane byte clock cycles
|
||||
* @param active_width Horizontal active width, in lane byte clock cycles
|
||||
* @param hfp Horizontal Front Porch period, in lane byte clock cycles
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_dpi_set_horizontal_timing(dsi_host_dev_t *dev, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp)
|
||||
{
|
||||
dev->vid_hsa_time.vid_hsa_time = hsw;
|
||||
dev->vid_hbp_time.vid_hbp_time = hbp;
|
||||
// the vid_hline_time here is the overall time for each video line
|
||||
dev->vid_hline_time.vid_hline_time = active_width + hsw + hbp + hfp;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Enable the tearing effect acknowledge
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_te_ack(dsi_host_dev_t *dev, bool en)
|
||||
{
|
||||
dev->cmd_mode_cfg.tear_fx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the acknowledge request after each packet transmission
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_cmd_ack(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->cmd_mode_cfg.ack_rqst_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode when transmitting DCS short write commands
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param num_of_params Number of parameters in the DCS command
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_dcs_short_wr_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
switch (num_of_params) {
|
||||
case 0: // DCS short write command with no parameter
|
||||
dev->cmd_mode_cfg.dcs_sw_0p_tx = speed;
|
||||
break;
|
||||
case 1: // DCS short write command with one parameter
|
||||
dev->cmd_mode_cfg.dcs_sw_1p_tx = speed;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode when transmitting DCS long write commands
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_dcs_long_wr_speed_mode(dsi_host_dev_t *dev, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
dev->cmd_mode_cfg.dcs_lw_tx = speed;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode when transmitting DCS read commands
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param num_of_params Number of parameters in the DCS command
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_dcs_short_rd_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
switch (num_of_params) {
|
||||
case 0: // DCS short read with zero parameter
|
||||
dev->cmd_mode_cfg.dcs_sr_0p_tx = speed;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode when transmitting generic short write commands
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param num_of_params Number of parameters in the generic command
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_gen_short_wr_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
switch (num_of_params) {
|
||||
case 0: // Generic short write command with no parameter
|
||||
dev->cmd_mode_cfg.gen_sw_0p_tx = speed;
|
||||
break;
|
||||
case 1: // Generic short write command with one parameter
|
||||
dev->cmd_mode_cfg.gen_sw_1p_tx = speed;
|
||||
break;
|
||||
case 2: // Generic short write command with two parameters
|
||||
dev->cmd_mode_cfg.gen_sw_2p_tx = speed;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode when transmitting generic long write commands
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_gen_long_wr_speed_mode(dsi_host_dev_t *dev, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
dev->cmd_mode_cfg.gen_lw_tx = speed;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode when transmitting generic short read commands
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param num_of_params Number of parameters in the generic command
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_gen_short_rd_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
switch (num_of_params) {
|
||||
case 0: // Generic short read command with zero parameter
|
||||
dev->cmd_mode_cfg.gen_sr_0p_tx = speed;
|
||||
break;
|
||||
case 1: // Generic short read command with one parameter
|
||||
dev->cmd_mode_cfg.gen_sr_1p_tx = speed;
|
||||
break;
|
||||
case 2: // Generic short read command with two parameters
|
||||
dev->cmd_mode_cfg.gen_sr_2p_tx = speed;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the speed mode for the "Maximum Return Packet Size" command
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param speed Speed mode
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_mrps_speed_mode(dsi_host_dev_t *dev, mipi_dsi_ll_trans_speed_mode_t speed)
|
||||
{
|
||||
dev->cmd_mode_cfg.max_rd_pkt_size = speed;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable receive EoT packet
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_rx_eotp(dsi_host_dev_t *dev, bool en)
|
||||
{
|
||||
dev->pckhdl_cfg.eotp_rx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable transmit EoT packet
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable_in_hs_mode True to enable, False to disable
|
||||
* @param enable_in_lp_mode True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_tx_eotp(dsi_host_dev_t *dev, bool enable_in_hs_mode, bool enable_in_lp_mode)
|
||||
{
|
||||
dev->pckhdl_cfg.eotp_tx_en = enable_in_hs_mode;
|
||||
dev->pckhdl_cfg.eotp_tx_lp_en = enable_in_lp_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the CRC check for the received packets
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_rx_crc(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->pckhdl_cfg.crc_rx_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the ECC check for the received packets
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_rx_ecc(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->pckhdl_cfg.ecc_rx_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Bus Turn Around (BTA) request
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_enable_bta(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->pckhdl_cfg.bta_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the timing for low power commands sent while in video mode
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param in_vact largest packet size during VACT period, in bytes
|
||||
* @param out_vact largest packet size during non-VACT period (VSA,VBP,VFP), in bytes
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_set_lp_largest_cmd_packet_size(dsi_host_dev_t *dev, uint32_t in_vact, uint32_t out_vact)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->dpi_lp_cmd_tim, invact_lpcmd_time, in_vact);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->dpi_lp_cmd_tim, outvact_lpcmd_time, out_vact);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////Generic Interface///////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the header for new packets sent using the Generic interface
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param dt Data type
|
||||
* @param vc_id Virtual channel ID
|
||||
* @param ms_byte most significant byte of the word count for long packets or data1 for short packets
|
||||
* @param ls_byte least significant byte of the word count for long packets or data0 for short packets
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_gen_set_packet_header(dsi_host_dev_t *dev, uint8_t vc_id,
|
||||
mipi_dsi_data_type_t dt, uint8_t ms_byte, uint8_t ls_byte)
|
||||
{
|
||||
dev->gen_hdr.val = (ms_byte << 16) | (ls_byte << 8) | ((vc_id << 6) | dt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the payload for packets sent using the generic interface
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param payload Payload data
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_gen_write_payload_fifo(dsi_host_dev_t *dev, uint32_t payload)
|
||||
{
|
||||
dev->gen_pld_data.val = payload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief When using the generic interface, return the contents of READ responses
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return payload data
|
||||
*/
|
||||
static inline uint32_t mipi_dsi_host_ll_gen_read_payload_fifo(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->gen_pld_data.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the read command of the generic interface busy?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if busy, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_read_cmd_busy(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_rd_cmd_busy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the read payload FIFO of the generic interface full?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if full, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_read_fifo_full(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_pld_r_full;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the read payload FIFO of the generic interface empty?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if empty, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_read_fifo_empty(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_pld_r_empty;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the write payload FIFO of generic interface full?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if full, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_write_fifo_full(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_pld_w_full;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the write payload FIFO of generic interface empty?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if empty, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_write_fifo_empty(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_pld_w_empty;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the command FIFO of generic interface full?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if full, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_cmd_fifo_full(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_cmd_full;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Is the command FIFO of generic interface empty?
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if empty, False if not
|
||||
*/
|
||||
static inline bool mipi_dsi_host_ll_gen_is_cmd_fifo_empty(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->cmd_pkt_status.gen_cmd_empty;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the ID of the virtual channel that for generic reading back
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param vcid Virtual channel ID
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_gen_set_rx_vcid(dsi_host_dev_t *dev, uint32_t vcid)
|
||||
{
|
||||
dev->gen_vcid.gen_vcid_rx = vcid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the ID of the virtual channel that for tear effect
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param vcid Virtual channel ID
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_gen_set_te_vcid(dsi_host_dev_t *dev, uint32_t vcid)
|
||||
{
|
||||
dev->gen_vcid.gen_vcid_tear_auto = vcid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the ID of the virtual channel that for automatically transmitting generic packets
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param vcid Virtual channel ID
|
||||
*/
|
||||
static inline void mipi_dsi_host_ll_gen_set_tx_vcid(dsi_host_dev_t *dev, uint32_t vcid)
|
||||
{
|
||||
dev->gen_vcid.gen_vcid_tx_auto = vcid;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
}
|
||||
#endif
|
||||
175
components/hal/esp32p4/include/hal/mipi_dsi_ll.h
Normal file
175
components/hal/esp32p4/include/hal/mipi_dsi_ll.h
Normal file
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/mipi_dsi_host_ll.h"
|
||||
#include "hal/mipi_dsi_brg_ll.h"
|
||||
#include "hal/mipi_dsi_phy_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the bus clock for MIPI DSI module
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param enable true to enable, false to disable
|
||||
*/
|
||||
static inline void mipi_dsi_ll_enable_bus_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.soc_clk_ctrl1.reg_dsi_sys_clk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_bus_clock(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Reset the MIPI DSI module
|
||||
*
|
||||
* @param group_id Group ID
|
||||
*/
|
||||
static inline void mipi_dsi_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dsi_brg = 1;
|
||||
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dsi_brg = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_reset_register(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Enable MIPI DSI DPI clock
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param enable true to enable, false to disable
|
||||
*/
|
||||
static inline void mipi_dsi_ll_enable_dpi_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_enable_dpi_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_dpi_clock(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the DSI DPI interface
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param source Clock source
|
||||
*/
|
||||
static inline void mipi_dsi_ll_set_dpi_clock_source(int group_id, mipi_dsi_dpi_clock_source_t source)
|
||||
{
|
||||
(void)group_id;
|
||||
switch (source) {
|
||||
case MIPI_DSI_DPI_CLK_SRC_XTAL:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 0;
|
||||
break;
|
||||
case MIPI_DSI_DPI_CLK_SRC_PLL_F160M:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 2;
|
||||
break;
|
||||
case MIPI_DSI_DPI_CLK_SRC_PLL_F240M:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_set_dpi_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_dpi_clock_source(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Set the clock division factor for the DPI clock source
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param div Division factor
|
||||
*/
|
||||
static inline void mipi_dsi_ll_set_dpi_clock_div(int group_id, uint32_t div)
|
||||
{
|
||||
(void)group_id;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl03, reg_mipi_dsi_dpiclk_div_num, div - 1);
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_set_dpi_clock_div(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_dpi_clock_div(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Enable MIPI DSI PHY configuration clock
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param enable true to enable, false to disable
|
||||
*/
|
||||
static inline void mipi_dsi_ll_enable_phy_config_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_cfg_clk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_enable_phy_config_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_phy_config_clock(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Enable MIPI DSI PHY PLL reference clock
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param enable true to enable, false to disable
|
||||
*/
|
||||
static inline void mipi_dsi_ll_enable_phy_reference_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_enable_phy_reference_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_phy_reference_clock(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the DSI PHY interface
|
||||
*
|
||||
* @param group_id Group ID
|
||||
* @param source Clock source
|
||||
*/
|
||||
static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_clock_source_t source)
|
||||
{
|
||||
(void)group_id;
|
||||
switch (source) {
|
||||
case MIPI_DSI_PHY_CLK_SRC_PLL_F20M:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0;
|
||||
break;
|
||||
case MIPI_DSI_PHY_CLK_SRC_RC_FAST:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1;
|
||||
break;
|
||||
case MIPI_DSI_PHY_CLK_SRC_PLL_F25M:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mipi_dsi_ll_set_phy_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_phy_clock_source(__VA_ARGS__)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
234
components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h
Normal file
234
components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h
Normal file
@@ -0,0 +1,234 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "soc/mipi_dsi_host_struct.h"
|
||||
#include "hal/mipi_dsi_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the PHY clock lane
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_enable_clock_lane(dsi_host_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->phy_rstz.phy_enableclk = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the digital section of the PHY
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to place the PHY in the reset state, False to release the reset
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_reset(dsi_host_dev_t *dev)
|
||||
{
|
||||
dev->phy_rstz.phy_rstz = 0;
|
||||
dev->phy_rstz.phy_rstz = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Shutdown the PHY
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param on_off True to power up, false to shut down
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_power_on_off(dsi_host_dev_t *dev, bool on_off)
|
||||
{
|
||||
dev->phy_rstz.phy_shutdownz = on_off;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Force the PHY to stay on while in ULPS
|
||||
*
|
||||
* @note To follow the programming model, use wakeup_pll function
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_force_pll(dsi_host_dev_t *dev, bool force)
|
||||
{
|
||||
dev->phy_rstz.phy_forcepll = force;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the PHY PLL is locked
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if the PLL is locked, False otherwise
|
||||
*/
|
||||
static inline bool mipi_dsi_phy_ll_is_pll_locked(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->phy_status.phy_lock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the Lane0 in stop state
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @return True if the Lane0 in stop state, False otherwise
|
||||
*/
|
||||
static inline bool mipi_dsi_phy_ll_is_lane0_stoped(dsi_host_dev_t *dev)
|
||||
{
|
||||
return dev->phy_status.phy_stopstate0lane;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of active data lanes
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param lane_num Number of lanes used in the DSI link
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_set_data_lane_number(dsi_host_dev_t *dev, uint32_t lane_num)
|
||||
{
|
||||
dev->phy_if_cfg.n_lanes = lane_num - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the minimum time PHY needs to stay in Stop state before requesting an HS transmission
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param wait_time Time in lane byte clock cycles
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_set_stop_wait_time(dsi_host_dev_t *dev, uint32_t wait_time)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->phy_if_cfg, phy_stop_wait_time, wait_time);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the maximum time required to perform a read command in lane byte clock cycles
|
||||
*
|
||||
* @note This can only be modified when no read command is in progress
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param max_time Maximum time required to perform a read command in lane byte clock cycles
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_set_max_read_time(dsi_host_dev_t *dev, uint32_t max_time)
|
||||
{
|
||||
dev->phy_tmr_rd_cfg.max_rd_time = max_time;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ULPS mode request on all active data lanes
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_data_enter_ulps(dsi_host_dev_t *dev)
|
||||
{
|
||||
dev->phy_ulps_ctrl.phy_txrequlpslan = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ULPS mode exit on all active data lanes
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_data_exit_ulps(dsi_host_dev_t *dev)
|
||||
{
|
||||
dev->phy_ulps_ctrl.phy_txexitulpslan = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ULPS mode request on clock lane
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_clk_enter_ulps(dsi_host_dev_t *dev)
|
||||
{
|
||||
dev->phy_ulps_ctrl.phy_txrequlpsclk = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ULPS mode exit on clock lane
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_clk_exit_ulps(dsi_host_dev_t *dev)
|
||||
{
|
||||
dev->phy_ulps_ctrl.phy_txexitulpsclk = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Control the internal interface (clock and pins) between the DSI Host and the D-PHY
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param clock_level Level of the clock
|
||||
* @param clear Whether to clear the pins of the PHY
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_write_clock(dsi_host_dev_t *dev, uint32_t clock_level, bool clear)
|
||||
{
|
||||
dev->phy_tst_ctrl0.val = clock_level << 1 | clear;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the PHY register via internal interface (so-called the test interface)
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param reg_addr Address of the PHY register
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_write_reg_addr(dsi_host_dev_t *dev, uint8_t reg_addr)
|
||||
{
|
||||
dev->phy_tst_ctrl1.val = (1 << 16) | (reg_addr & 0xFF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the PHY register value via internal interface (so-called the test interface)
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param reg_val Value to write to the PHY register
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_write_reg_val(dsi_host_dev_t *dev, uint8_t reg_val)
|
||||
{
|
||||
dev->phy_tst_ctrl1.val = reg_val & 0xFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send trigger transmission
|
||||
*
|
||||
* @note Only one bit of the trigger_request is asserted at a time
|
||||
* @note Only call this function when the PHY is not in LPDT or ULPS modes
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param trigger_request Trigger request
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_escape_trigger(dsi_host_dev_t *dev, uint8_t trigger_request)
|
||||
{
|
||||
dev->phy_tx_triggers.phy_tx_triggers = trigger_request;
|
||||
while (dev->phy_status.phy_stopstate0lane == 0);
|
||||
dev->phy_tx_triggers.phy_tx_triggers = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the time to switch between HS and LP
|
||||
*
|
||||
* @param dev Pointer to the DSI Host controller register base address
|
||||
* @param data_hs2lp Time to switch data lane from HS to LP, in lane byte clock cycles
|
||||
* @param data_lp2hs Time to switch data lane from LP to HS, in lane byte clock cycles
|
||||
* @param clk_hs2lp Time to switch clock lane from HS to LP, in lane byte clock cycles
|
||||
* @param clk_lp2hs Time to switch clock lane from LP to HS, in lane byte clock cycles
|
||||
*/
|
||||
static inline void mipi_dsi_phy_ll_set_switch_time(dsi_host_dev_t *dev, uint32_t data_hs2lp, uint32_t data_lp2hs, uint32_t clk_hs2lp, uint32_t clk_lp2hs)
|
||||
{
|
||||
dev->phy_tmr_cfg.phy_hs2lp_time = data_hs2lp;
|
||||
dev->phy_tmr_cfg.phy_lp2hs_time = data_lp2hs;
|
||||
dev->phy_tmr_lpclk_cfg.phy_clkhs2lp_time = clk_hs2lp;
|
||||
dev->phy_tmr_lpclk_cfg.phy_clklp2hs_time = clk_lp2hs;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user