mirror of
https://github.com/espressif/esp-idf.git
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esp32: move dport_access
This commit is contained in:
Renz Bagaporo
committed by
Michael (XIAO Xufeng)
Michael (XIAO Xufeng)
parent
702e41e1c8
commit
452bfda367
@@ -13,7 +13,6 @@ else()
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# Regular app build
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set(srcs
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"cache_sram_mmu.c"
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"dport_access.c"
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"esp_himem.c"
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"spiram.c"
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"spiram_psram.c")
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@@ -1,296 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
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* This function will be initialize after FreeRTOS startup.
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* When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
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* cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_periph.h"
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#include "hal/cpu_hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "sdkconfig.h"
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#ifndef CONFIG_FREERTOS_UNICORE
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static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
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#define DPORT_CORE_STATE_IDLE 0
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#define DPORT_CORE_STATE_RUNNING 1
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static uint32_t volatile dport_core_state[portNUM_PROCESSORS]; //cpu is already run
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/* these global variables are accessed from interrupt vector, hence not declared as static */
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uint32_t volatile dport_access_start[portNUM_PROCESSORS]; //dport register could be accessed
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uint32_t volatile dport_access_end[portNUM_PROCESSORS]; //dport register is accessed over
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static uint32_t volatile dport_access_ref[portNUM_PROCESSORS]; //dport access reference
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#ifdef DPORT_ACCESS_BENCHMARK
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#define DPORT_ACCESS_BENCHMARK_STORE_NUM
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static uint32_t ccount_start[portNUM_PROCESSORS];
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static uint32_t ccount_end[portNUM_PROCESSORS];
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static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM];
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static uint32_t ccount_margin_cnt;
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#endif
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static BaseType_t oldInterruptLevel[2];
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#endif // CONFIG_FREERTOS_UNICORE
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/* stall other cpu that this cpu is pending to access dport register start */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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BaseType_t intLvl = portENTER_CRITICAL_NESTED();
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int cpu_id = xPortGetCoreID();
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_start[cpu_id] = cpu_hal_get_cycle_count();
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#endif
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if (dport_access_ref[cpu_id] == 0) {
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portENTER_CRITICAL_ISR(&g_dport_mux);
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oldInterruptLevel[cpu_id]=intLvl;
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dport_access_start[cpu_id] = 0;
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dport_access_end[cpu_id] = 0;
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if (cpu_id == 0) {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
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} else {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
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}
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while (!dport_access_start[cpu_id]) {};
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REG_READ(SPI_DATE_REG(3)); //just read a APB register sure that the APB-bus is idle
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}
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dport_access_ref[cpu_id]++;
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if (dport_access_ref[cpu_id] > 1) {
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/* Interrupts are already disabled by the parent, we're nested here. */
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portEXIT_CRITICAL_NESTED(intLvl);
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}
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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/* stall other cpu that this cpu is pending to access dport register end */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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int cpu_id = xPortGetCoreID();
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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if (dport_access_ref[cpu_id] == 0) {
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assert(0);
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}
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dport_access_ref[cpu_id]--;
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if (dport_access_ref[cpu_id] == 0) {
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dport_access_end[cpu_id] = 1;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
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}
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_end[cpu_id] = cpu_hal_get_cycle_count();
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ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
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ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
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#endif
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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static void dport_access_init_core(void *arg)
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{
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int core_id = 0;
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uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
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core_id = xPortGetCoreID();
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if (core_id == 1) {
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intr_source = ETS_FROM_CPU_INTR3_SOURCE;
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}
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ESP_INTR_DISABLE(ETS_DPORT_INUM);
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intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
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ESP_INTR_ENABLE(ETS_DPORT_INUM);
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dport_access_ref[core_id] = 0;
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dport_access_start[core_id] = 0;
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dport_access_end[core_id] = 0;
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dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
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/* If this fails then the minimum stack size for this config is too close to running out */
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assert(uxTaskGetStackHighWaterMark(NULL) > 128);
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vTaskDelete(NULL);
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}
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#endif
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/* Defer initialisation until after scheduler is running */
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void esp_dport_access_int_init(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
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assert(res == pdTRUE);
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(void)res;
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_pause(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
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void IRAM_ATTR esp_dport_access_int_abort(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_resume(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
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dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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/**
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* @brief Read a sequence of DPORT registers to the buffer, SMP-safe version.
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*
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* This implementation uses a method of the pre-reading of the APB register
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* before reading the register of the DPORT, without stall other CPU.
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* There is disable/enable interrupt.
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*
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* @param[out] buff_out Contains the read data.
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* @param[in] address Initial address for reading registers.
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* @param[in] num_words The number of words.
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*/
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void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
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{
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DPORT_INTERRUPT_DISABLE();
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for (uint32_t i = 0; i < num_words; ++i) {
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buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4);
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}
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DPORT_INTERRUPT_RESTORE();
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}
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/**
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* @brief Read value from register, SMP-safe version.
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*
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* This method uses the pre-reading of the APB register before reading the register of the DPORT.
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* This implementation is useful for reading DORT registers for single reading without stall other CPU.
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* There is disable/enable interrupt.
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*
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* @param reg Register address
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* @return Value
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*/
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uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
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{
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#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
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return _DPORT_REG_READ(reg);
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#else
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uint32_t apb;
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unsigned int intLvl;
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__asm__ __volatile__ (\
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"rsil %[LVL], "XTSTR(CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL)"\n"\
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"movi %[APB], "XTSTR(0x3ff40078)"\n"\
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"l32i %[APB], %[APB], 0\n"\
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"l32i %[REG], %[REG], 0\n"\
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"wsr %[LVL], "XTSTR(PS)"\n"\
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"rsync\n"\
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: [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
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: \
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: "memory" \
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);
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return reg;
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#endif
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}
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/**
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* @brief Read value from register, NOT SMP-safe version.
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*
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* This method uses the pre-reading of the APB register before reading the register of the DPORT.
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* There is not disable/enable interrupt.
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* The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading.
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* This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example.
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* The recommended way to read registers sequentially without stall other CPU
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* is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer.
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*
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* \code{c}
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* // This example shows how to use it.
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* { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE.
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* DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
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* for (i = 0; i < max; ++i) {
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* array[i] = esp_dport_access_sequence_reg_read(Address + i * 4); // reading DPORT registers
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* }
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* DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
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* }
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* \endcode
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*
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* @param reg Register address
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* @return Value
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*/
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uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
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{
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#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
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return _DPORT_REG_READ(reg);
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#else
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uint32_t apb;
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__asm__ __volatile__ (\
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"movi %[APB], "XTSTR(0x3ff40078)"\n"\
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"l32i %[APB], %[APB], 0\n"\
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"l32i %[REG], %[REG], 0\n"\
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: [APB]"=a"(apb), [REG]"+a"(reg)\
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: \
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: "memory" \
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);
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return reg;
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#endif
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}
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@@ -1,47 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <sdkconfig.h>
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#ifndef _ESP_DPORT_ACCESS_H_
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#define _ESP_DPORT_ACCESS_H_
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#include "xtensa/xtruntime.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void esp_dport_access_stall_other_cpu_start(void);
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void esp_dport_access_stall_other_cpu_end(void);
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void esp_dport_access_int_init(void);
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void esp_dport_access_int_pause(void);
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void esp_dport_access_int_resume(void);
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void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
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uint32_t esp_dport_access_reg_read(uint32_t reg);
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uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
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//This routine does not stop the dport routines in any way that is recoverable. Please
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//only call in case of panic().
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void esp_dport_access_int_abort(void);
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#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
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#define DPORT_STALL_OTHER_CPU_START()
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#define DPORT_STALL_OTHER_CPU_END()
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#define DPORT_INTERRUPT_DISABLE()
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#define DPORT_INTERRUPT_RESTORE()
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#else
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#define DPORT_STALL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STALL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#define DPORT_INTERRUPT_DISABLE() unsigned int intLvl = XTOS_SET_INTLEVEL(CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL)
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#define DPORT_INTERRUPT_RESTORE() XTOS_RESTORE_JUST_INTLEVEL(intLvl)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ESP_DPORT_ACCESS_H_ */
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@@ -1,503 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include "xtensa/core-macros.h"
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#include "xtensa/hal.h"
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#include "esp_types.h"
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#include "esp32/clk.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_timer.h"
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#include "soc/cpu.h"
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#include "unity.h"
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#include "test_utils.h"
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#include "esp_rom_uart.h"
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#include "hal/uart_types.h"
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#include "hal/uart_ll.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc.h"
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#include "hal/cpu_hal.h"
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#include "esp_intr_alloc.h"
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#include "driver/timer.h"
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#define MHZ (1000000)
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static volatile bool exit_flag;
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static bool dport_test_result;
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static bool apb_test_result;
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uint32_t volatile apb_intr_test_result;
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static void accessDPORT(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t dport_date = DPORT_REG_READ(DPORT_DATE_REG);
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dport_test_result = true;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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if (dport_date != DPORT_REG_READ(DPORT_DATE_REG)) {
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dport_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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static void accessAPB(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t uart_date = REG_READ(UART_DATE_REG(0));
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apb_test_result = true;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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if (uart_date != REG_READ(UART_DATE_REG(0))) {
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apb_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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void run_tasks(const char *task1_description, void (* task1_func)(void *), const char *task2_description, void (* task2_func)(void *), uint32_t delay_ms)
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{
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apb_intr_test_result = 1;
|
||||
int i;
|
||||
TaskHandle_t th[2];
|
||||
xSemaphoreHandle exit_sema[2];
|
||||
|
||||
for (i=0; i<2; i++) {
|
||||
if((task1_func != NULL && i == 0) || (task2_func != NULL && i == 1)){
|
||||
exit_sema[i] = xSemaphoreCreateBinary();
|
||||
}
|
||||
}
|
||||
|
||||
exit_flag = false;
|
||||
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
printf("assign task accessing DPORT to core 0 and task accessing APB to core 1\n");
|
||||
if(task1_func != NULL) xTaskCreatePinnedToCore(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0], 0);
|
||||
if(task2_func != NULL) xTaskCreatePinnedToCore(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1], 1);
|
||||
#else
|
||||
printf("assign task accessing DPORT and accessing APB\n");
|
||||
if(task1_func != NULL) xTaskCreate(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0]);
|
||||
if(task2_func != NULL) xTaskCreate(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1]);
|
||||
#endif
|
||||
|
||||
printf("start wait for %d seconds [Test %s and %s]\n", delay_ms/1000, task1_description, task2_description);
|
||||
vTaskDelay(delay_ms / portTICK_PERIOD_MS);
|
||||
|
||||
// set exit flag to let thread exit
|
||||
exit_flag = true;
|
||||
|
||||
for (i=0; i<2; i++) {
|
||||
if ((task1_func != NULL && i == 0) || (task2_func != NULL && i == 1)) {
|
||||
xSemaphoreTake(exit_sema[i], portMAX_DELAY);
|
||||
vSemaphoreDelete(exit_sema[i]);
|
||||
}
|
||||
}
|
||||
TEST_ASSERT(dport_test_result == true && apb_test_result == true && apb_intr_test_result == 1);
|
||||
}
|
||||
|
||||
TEST_CASE("access DPORT and APB at same time", "[esp32]")
|
||||
{
|
||||
dport_test_result = false;
|
||||
apb_test_result = false;
|
||||
printf("CPU_FREQ = %d MHz\n", esp_clk_cpu_freq());
|
||||
run_tasks("accessDPORT", accessDPORT, "accessAPB", accessAPB, 10000);
|
||||
}
|
||||
|
||||
void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
|
||||
{
|
||||
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
|
||||
const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
|
||||
dport_test_result = false;
|
||||
apb_test_result = false;
|
||||
rtc_cpu_freq_config_t old_config;
|
||||
rtc_clk_cpu_freq_get_config(&old_config);
|
||||
|
||||
printf("CPU_FREQ = %d MHz\n", old_config.freq_mhz);
|
||||
|
||||
if (cpu_freq_mhz != old_config.freq_mhz) {
|
||||
rtc_cpu_freq_config_t new_config;
|
||||
bool res = rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &new_config);
|
||||
assert(res && "invalid frequency value");
|
||||
|
||||
esp_rom_uart_tx_wait_idle(uart_num);
|
||||
rtc_clk_cpu_freq_set_config(&new_config);
|
||||
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_APB);
|
||||
uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud);
|
||||
/* adjust RTOS ticks */
|
||||
_xt_tick_divisor = cpu_freq_mhz * 1000000 / XT_TICK_PER_SEC;
|
||||
vTaskDelay(2);
|
||||
|
||||
printf("CPU_FREQ switched to %d MHz\n", cpu_freq_mhz);
|
||||
}
|
||||
run_tasks("accessDPORT", accessDPORT, "accessAPB", accessAPB, 10000);
|
||||
|
||||
// return old freq.
|
||||
esp_rom_uart_tx_wait_idle(uart_num);
|
||||
rtc_clk_cpu_freq_set_config(&old_config);
|
||||
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_APB);
|
||||
uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud);
|
||||
_xt_tick_divisor = old_config.freq_mhz * 1000000 / XT_TICK_PER_SEC;
|
||||
}
|
||||
|
||||
TEST_CASE("access DPORT and APB at same time (Freq CPU and APB = 80 MHz)", "[esp32] [ignore]")
|
||||
{
|
||||
run_tasks_with_change_freq_cpu(80);
|
||||
}
|
||||
|
||||
TEST_CASE("access DPORT and APB at same time (Freq CPU and APB = 40 MHz (XTAL))", "[esp32]")
|
||||
{
|
||||
run_tasks_with_change_freq_cpu((int) rtc_clk_xtal_freq_get());
|
||||
}
|
||||
|
||||
static uint32_t stall_other_cpu_counter;
|
||||
static uint32_t pre_reading_apb_counter;
|
||||
static uint32_t apb_counter;
|
||||
|
||||
static void accessDPORT_stall_other_cpu(void *pvParameters)
|
||||
{
|
||||
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
||||
uint32_t dport_date = DPORT_REG_READ(DPORT_DATE_REG);
|
||||
uint32_t dport_date_cur;
|
||||
dport_test_result = true;
|
||||
stall_other_cpu_counter = 0;
|
||||
// although exit flag is set in another task, checking (exit_flag == false) is safe
|
||||
while (exit_flag == false) {
|
||||
++stall_other_cpu_counter;
|
||||
DPORT_STALL_OTHER_CPU_START();
|
||||
dport_date_cur = _DPORT_REG_READ(DPORT_DATE_REG);
|
||||
DPORT_STALL_OTHER_CPU_END();
|
||||
if (dport_date != dport_date_cur) {
|
||||
apb_test_result = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
xSemaphoreGive(*sema);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
static void accessAPB_measure_performance(void *pvParameters)
|
||||
{
|
||||
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
||||
uint32_t uart_date = REG_READ(UART_DATE_REG(0));
|
||||
|
||||
apb_test_result = true;
|
||||
apb_counter = 0;
|
||||
// although exit flag is set in another task, checking (exit_flag == false) is safe
|
||||
while (exit_flag == false) {
|
||||
++apb_counter;
|
||||
if (uart_date != REG_READ(UART_DATE_REG(0))) {
|
||||
apb_test_result = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
xSemaphoreGive(*sema);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
static void accessDPORT_pre_reading_apb(void *pvParameters)
|
||||
{
|
||||
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
||||
uint32_t dport_date = DPORT_REG_READ(DPORT_DATE_REG);
|
||||
uint32_t dport_date_cur;
|
||||
dport_test_result = true;
|
||||
pre_reading_apb_counter = 0;
|
||||
// although exit flag is set in another task, checking (exit_flag == false) is safe
|
||||
while (exit_flag == false) {
|
||||
++pre_reading_apb_counter;
|
||||
dport_date_cur = DPORT_REG_READ(DPORT_DATE_REG);
|
||||
if (dport_date != dport_date_cur) {
|
||||
apb_test_result = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
xSemaphoreGive(*sema);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
TEST_CASE("test for DPORT access performance", "[esp32]")
|
||||
{
|
||||
dport_test_result = true;
|
||||
apb_test_result = true;
|
||||
typedef struct {
|
||||
uint32_t dport;
|
||||
uint32_t apb;
|
||||
uint32_t summ;
|
||||
} test_performance_t;
|
||||
test_performance_t t[5] = {0};
|
||||
uint32_t delay_ms = 5000;
|
||||
|
||||
run_tasks("-", NULL, "accessAPB", accessAPB_measure_performance, delay_ms);
|
||||
t[0].apb = apb_counter;
|
||||
t[0].dport = 0;
|
||||
t[0].summ = t[0].apb + t[0].dport;
|
||||
|
||||
run_tasks("accessDPORT_stall_other_cpu", accessDPORT_stall_other_cpu, "-", NULL, delay_ms);
|
||||
t[1].apb = 0;
|
||||
t[1].dport = stall_other_cpu_counter;
|
||||
t[1].summ = t[1].apb + t[1].dport;
|
||||
|
||||
run_tasks("accessDPORT_pre_reading_apb", accessDPORT_pre_reading_apb, "-", NULL, delay_ms);
|
||||
t[2].apb = 0;
|
||||
t[2].dport = pre_reading_apb_counter;
|
||||
t[2].summ = t[2].apb + t[2].dport;
|
||||
|
||||
run_tasks("accessDPORT_stall_other_cpu", accessDPORT_stall_other_cpu, "accessAPB", accessAPB_measure_performance, delay_ms);
|
||||
t[3].apb = apb_counter;
|
||||
t[3].dport = stall_other_cpu_counter;
|
||||
t[3].summ = t[3].apb + t[3].dport;
|
||||
|
||||
run_tasks("accessDPORT_pre_reading_apb", accessDPORT_pre_reading_apb, "accessAPB", accessAPB_measure_performance, delay_ms);
|
||||
t[4].apb = apb_counter;
|
||||
t[4].dport = pre_reading_apb_counter;
|
||||
t[4].summ = t[4].apb + t[4].dport;
|
||||
|
||||
printf("\nPerformance table: \n"
|
||||
"The number of simultaneous read operations of the APB and DPORT registers\n"
|
||||
"by different methods for %d seconds.\n", delay_ms/1000);
|
||||
printf("+-----------------------+----------+----------+----------+\n");
|
||||
printf("| Method read DPORT | DPORT | APB | SUMM |\n");
|
||||
printf("+-----------------------+----------+----------+----------+\n");
|
||||
printf("|1.Only accessAPB |%10d|%10d|%10d|\n", t[0].dport, t[0].apb, t[0].summ);
|
||||
printf("|2.Only STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[1].dport, t[1].apb, t[1].summ);
|
||||
printf("|3.Only PRE_READ_APB_REG|%10d|%10d|%10d|\n", t[2].dport, t[2].apb, t[2].summ);
|
||||
printf("+-----------------------+----------+----------+----------+\n");
|
||||
printf("|4.STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[3].dport, t[3].apb, t[3].summ);
|
||||
printf("|5.PRE_READ_APB_REG |%10d|%10d|%10d|\n", t[4].dport, t[4].apb, t[4].summ);
|
||||
printf("+-----------------------+----------+----------+----------+\n");
|
||||
printf("| ratio=PRE_READ/STALL |%10f|%10f|%10f|\n", (float)t[4].dport/t[3].dport, (float)t[4].apb/t[3].apb, (float)t[4].summ/t[3].summ);
|
||||
printf("+-----------------------+----------+----------+----------+\n");
|
||||
}
|
||||
|
||||
#define REPEAT_OPS 10000
|
||||
|
||||
static uint32_t start, end;
|
||||
|
||||
#define BENCHMARK_START() do { \
|
||||
RSR(CCOUNT, start); \
|
||||
} while(0)
|
||||
|
||||
#define BENCHMARK_END(OPERATION) do { \
|
||||
RSR(CCOUNT, end); \
|
||||
printf("%s took %d cycles/op (%d cycles for %d ops)\n", \
|
||||
OPERATION, (end - start)/REPEAT_OPS, \
|
||||
(end - start), REPEAT_OPS); \
|
||||
} while(0)
|
||||
|
||||
TEST_CASE("BENCHMARK for DPORT access performance", "[freertos]")
|
||||
{
|
||||
BENCHMARK_START();
|
||||
for (int i = 0; i < REPEAT_OPS; i++) {
|
||||
DPORT_STALL_OTHER_CPU_START();
|
||||
_DPORT_REG_READ(DPORT_DATE_REG);
|
||||
DPORT_STALL_OTHER_CPU_END();
|
||||
}
|
||||
BENCHMARK_END("[old]DPORT access STALL OTHER CPU");
|
||||
|
||||
|
||||
BENCHMARK_START();
|
||||
for (int i = 0; i < REPEAT_OPS; i++) {
|
||||
DPORT_REG_READ(DPORT_DATE_REG);
|
||||
}
|
||||
BENCHMARK_END("[new]DPORT access PRE-READ APB REG");
|
||||
|
||||
|
||||
BENCHMARK_START();
|
||||
for (int i = 0; i < REPEAT_OPS; i++) {
|
||||
DPORT_SEQUENCE_REG_READ(DPORT_DATE_REG);
|
||||
}
|
||||
BENCHMARK_END("[seq]DPORT access PRE-READ APB REG");
|
||||
|
||||
|
||||
BENCHMARK_START();
|
||||
for (int i = 0; i < REPEAT_OPS; i++) {
|
||||
REG_READ(UART_DATE_REG(0));
|
||||
}
|
||||
BENCHMARK_END("REG_READ");
|
||||
|
||||
|
||||
BENCHMARK_START();
|
||||
for (int i = 0; i < REPEAT_OPS; i++) {
|
||||
_DPORT_REG_READ(DPORT_DATE_REG);
|
||||
}
|
||||
BENCHMARK_END("_DPORT_REG_READ");
|
||||
}
|
||||
|
||||
uint32_t xt_highint5_read_apb;
|
||||
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
timer_isr_handle_t inth;
|
||||
xSemaphoreHandle sync_sema;
|
||||
|
||||
static void init_hi_interrupt(void *arg)
|
||||
{
|
||||
printf("init hi_interrupt on CPU%d \n", xPortGetCoreID());
|
||||
TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
|
||||
while (exit_flag == false);
|
||||
esp_intr_free(inth);
|
||||
printf("disable hi_interrupt on CPU%d \n", xPortGetCoreID());
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
static void accessDPORT2_stall_other_cpu(void *pvParameters)
|
||||
{
|
||||
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
||||
dport_test_result = true;
|
||||
while (exit_flag == false) {
|
||||
DPORT_STALL_OTHER_CPU_START();
|
||||
XTHAL_SET_CCOMPARE(2, cpu_hal_get_cycle_count());
|
||||
xt_highint5_read_apb = 1;
|
||||
for (int i = 0; i < 200; ++i) {
|
||||
if (_DPORT_REG_READ(DPORT_DATE_REG) != _DPORT_REG_READ(DPORT_DATE_REG)) {
|
||||
apb_test_result = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
xt_highint5_read_apb = 0;
|
||||
DPORT_STALL_OTHER_CPU_END();
|
||||
}
|
||||
printf("accessDPORT2_stall_other_cpu finish\n");
|
||||
|
||||
xSemaphoreGive(*sema);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
TEST_CASE("Check stall workaround DPORT and Hi-interrupt", "[esp32]")
|
||||
{
|
||||
xt_highint5_read_apb = 0;
|
||||
dport_test_result = false;
|
||||
apb_test_result = true;
|
||||
TEST_ASSERT(xTaskCreatePinnedToCore(&init_hi_interrupt, "init_hi_intr", 2048, NULL, 6, NULL, 1) == pdTRUE);
|
||||
// Access DPORT(stall other cpu method) - CPU0
|
||||
// STALL - CPU1
|
||||
// Hi-interrupt - CPU1
|
||||
run_tasks("accessDPORT2_stall_other_cpu", accessDPORT2_stall_other_cpu, " - ", NULL, 10000);
|
||||
}
|
||||
|
||||
static void accessDPORT2(void *pvParameters)
|
||||
{
|
||||
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
||||
dport_test_result = true;
|
||||
|
||||
TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
|
||||
|
||||
while (exit_flag == false) {
|
||||
XTHAL_SET_CCOMPARE(2, cpu_hal_get_cycle_count() + 21);
|
||||
for (int i = 0; i < 200; ++i) {
|
||||
if (DPORT_REG_READ(DPORT_DATE_REG) != DPORT_REG_READ(DPORT_DATE_REG)) {
|
||||
dport_test_result = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
esp_intr_free(inth);
|
||||
printf("accessDPORT2 finish\n");
|
||||
|
||||
xSemaphoreGive(*sema);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
TEST_CASE("Check pre-read workaround DPORT and Hi-interrupt", "[esp32]")
|
||||
{
|
||||
xt_highint5_read_apb = 0;
|
||||
dport_test_result = false;
|
||||
apb_test_result = true;
|
||||
// Access DPORT(pre-read method) - CPU1
|
||||
// Hi-interrupt - CPU1
|
||||
run_tasks("accessAPB", accessAPB, "accessDPORT2", accessDPORT2, 10000);
|
||||
}
|
||||
|
||||
static uint32_t s_shift_counter;
|
||||
|
||||
/*
|
||||
The test_dport_access_reg_read() is similar DPORT_REG_READ() but has differents:
|
||||
- generate an interrupt by SET_CCOMPARE
|
||||
- additional branch command helps get good reproducing an issue with breaking the DPORT pre-read workaround
|
||||
- uncomment (1) and comment (2) it allows seeing the broken pre-read workaround
|
||||
For pre-reading the workaround, it is important that the two reading commands APB and DPORT
|
||||
are executed without interruption. For this reason, it disables interrupts and to do reading inside the safe area.
|
||||
But despite a disabling interrupt it was still possible that these two readings can be interrupted.
|
||||
The reason is linked with work parallel execution commands in the pipeline (it is not a bug).
|
||||
To resolve this issue (1) was moved to (2) position into the disabled interrupt part.
|
||||
When the read command is interrupted after stage E(execute), the result of its execution will be saved in the internal buffer,
|
||||
and after returning from the interrupt, this command takes this value from the buffer without repeating the reading,
|
||||
which is critical for the DPORT pre-read workaround. To fix it we added additional command under safe area ((1)->(2)).
|
||||
*/
|
||||
static uint32_t IRAM_ATTR test_dport_access_reg_read(uint32_t reg)
|
||||
{
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
return _DPORT_REG_READ(reg);
|
||||
#else
|
||||
uint32_t apb;
|
||||
unsigned int intLvl;
|
||||
XTHAL_SET_CCOMPARE(2, cpu_hal_get_cycle_count() + s_shift_counter);
|
||||
__asm__ __volatile__ (\
|
||||
/* "movi %[APB], "XTSTR(0x3ff40078)"\n" */ /* (1) uncomment for reproduce issue */ \
|
||||
"bnez %[APB], kl1\n" /* this branch command helps get good reproducing */ \
|
||||
"kl1:\n"\
|
||||
"rsil %[LVL], "XTSTR(CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL)"\n"\
|
||||
"movi %[APB], "XTSTR(0x3ff40078)"\n" /* (2) comment for reproduce issue */ \
|
||||
"l32i %[APB], %[APB], 0\n"\
|
||||
"l32i %[REG], %[REG], 0\n"\
|
||||
"wsr %[LVL], "XTSTR(PS)"\n"\
|
||||
"rsync\n"\
|
||||
: [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
|
||||
: \
|
||||
: "memory" \
|
||||
);
|
||||
return reg;
|
||||
#endif
|
||||
}
|
||||
|
||||
// The accessDPORT3 task is similar accessDPORT2 but uses test_dport_access_reg_read() instead of usual DPORT_REG_READ().
|
||||
static void accessDPORT3(void *pvParameters)
|
||||
{
|
||||
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
||||
dport_test_result = true;
|
||||
|
||||
TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
|
||||
int i = 0;
|
||||
while (exit_flag == false) {
|
||||
if (test_dport_access_reg_read(DPORT_DATE_REG) != test_dport_access_reg_read(DPORT_DATE_REG)) {
|
||||
dport_test_result = false;
|
||||
break;
|
||||
}
|
||||
if ((++i % 100) == 0) {
|
||||
s_shift_counter = (s_shift_counter + 1) % 30;
|
||||
}
|
||||
}
|
||||
esp_intr_free(inth);
|
||||
printf("accessDPORT3 finish\n");
|
||||
|
||||
xSemaphoreGive(*sema);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
TEST_CASE("Check pre-read workaround DPORT and Hi-interrupt (2)", "[esp32]")
|
||||
{
|
||||
s_shift_counter = 1;
|
||||
xt_highint5_read_apb = 0;
|
||||
dport_test_result = false;
|
||||
apb_test_result = true;
|
||||
// Access DPORT(pre-read method) - CPU1
|
||||
// Hi-interrupt - CPU1
|
||||
run_tasks("accessAPB", accessAPB, "accessDPORT3", accessDPORT3, 10000);
|
||||
}
|
||||
#endif // CONFIG_FREERTOS_UNICORE
|
||||
@@ -1,78 +0,0 @@
|
||||
#include <xtensa/coreasm.h>
|
||||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/system.h>
|
||||
#include "freertos/xtensa_context.h"
|
||||
#include "esp_private/panic_reason.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/dport_reg.h"
|
||||
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
|
||||
#define L5_INTR_STACK_SIZE 12
|
||||
#define L5_INTR_A2_OFFSET 0
|
||||
#define L5_INTR_A3_OFFSET 4
|
||||
#define L5_INTR_A4_OFFSET 8
|
||||
.data
|
||||
_l5_intr_stack:
|
||||
.space L5_INTR_STACK_SIZE
|
||||
|
||||
.section .iram1,"ax"
|
||||
.global xt_highint5
|
||||
.type xt_highint5,@function
|
||||
.align 4
|
||||
xt_highint5:
|
||||
|
||||
movi a0, xt_highint5_read_apb
|
||||
l32i a0, a0, 0
|
||||
bnez a0, .read_apb_reg
|
||||
|
||||
// Short interrupt
|
||||
movi a0, 0
|
||||
wsr a0, CCOMPARE2
|
||||
esync
|
||||
|
||||
rsr a0, EXCSAVE_5 // restore a0
|
||||
rfi 5
|
||||
|
||||
|
||||
|
||||
// read APB reg 10 time.
|
||||
.read_apb_reg:
|
||||
movi a0, _l5_intr_stack
|
||||
s32i a2, a0, L5_INTR_A2_OFFSET
|
||||
s32i a3, a0, L5_INTR_A3_OFFSET
|
||||
s32i a4, a0, L5_INTR_A4_OFFSET
|
||||
|
||||
movi a4, 10 // count of reading
|
||||
movi a0, 0x3ff40078 // read APB reg
|
||||
l32i a2, a0, 0
|
||||
.loop_read_apb_reg:
|
||||
l32i a3, a0, 0
|
||||
bne a3, a2, .need_set_apb_test_result
|
||||
addi a4, a4, -1
|
||||
l32i a2, a0, 0
|
||||
bnez a4, .loop_read_apb_reg
|
||||
j 1f
|
||||
.need_set_apb_test_result:
|
||||
movi a0, apb_intr_test_result // set fail
|
||||
movi a2, 0
|
||||
s32i a2, a0, 0
|
||||
memw
|
||||
1:
|
||||
movi a0, _l5_intr_stack
|
||||
l32i a2, a0, L5_INTR_A2_OFFSET
|
||||
l32i a3, a0, L5_INTR_A3_OFFSET
|
||||
l32i a4, a0, L5_INTR_A4_OFFSET
|
||||
rsync
|
||||
.L_xt_highint5_exit:
|
||||
rsr a0, EXCSAVE_5 // restore a0
|
||||
rfi 5
|
||||
|
||||
/* The linker has no reason to link in this file; all symbols it exports are already defined
|
||||
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
|
||||
linker inspect this anyway. */
|
||||
|
||||
.global ld_include_test_dport_xt_highint5
|
||||
ld_include_test_dport_xt_highint5:
|
||||
#endif // CONFIG_FREERTOS_UNICORE
|
||||
Reference in New Issue
Block a user