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feat(uart): add RCC atomic block to uart/lp-uart peripheral

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This commit is contained in:
gaoxu
2023-09-14 09:23:20 +08:00
parent c7afa0dcef
commit 4541ad134d
21 changed files with 643 additions and 168 deletions
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15
components/esp_pm/pm_impl.c
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@@ -17,6 +17,7 @@
#include "esp_cpu.h"
#include "esp_private/crosscore_int.h"
#include "esp_private/uart_private.h"
#include "soc/rtc.h"
#include "hal/uart_ll.h"
@@ -42,6 +43,7 @@
#include "esp_private/sleep_cpu.h"
#include "esp_private/sleep_gpio.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/periph_ctrl.h"
#include "esp_sleep.h"
#include "sdkconfig.h"
@@ -736,14 +738,19 @@ void esp_pm_impl_init(void)
#else
#error "No UART clock source is aware of DFS"
#endif // SOC_UART_SUPPORT_xxx
while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM)));
while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM))) {
;
}
/* When DFS is enabled, override system setting and use REFTICK as UART clock source */
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
UART_SCLK_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
}
uint32_t sclk_freq;
esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq);
assert(err == ESP_OK);
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
UART_SCLK_ATOMIC() {
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
}
#endif // CONFIG_ESP_CONSOLE_UART
#ifdef CONFIG_PM_TRACE