alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-18 23:54:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(uart): add RCC atomic block to uart/lp-uart peripheral

Browse Source
This commit is contained in:
gaoxu
2023-09-14 09:23:20 +08:00
parent c7afa0dcef
commit 4541ad134d
21 changed files with 643 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
components/hal/esp32s2/include/hal/uart_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,6 +15,8 @@
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/system_reg.h"
#include "soc/dport_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
@@ -53,6 +55,56 @@ typedef enum {
UART_INTR_WAKEUP = (0x1 << 19),
} uart_intr_t;
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
uint32_t reg_val = READ_PERI_REG(DPORT_PERIP_CLK_EN0_REG);
switch (uart_num)
{
case 0:
reg_val = reg_val & (~DPORT_UART_CLK_EN);
reg_val = reg_val | (enable << DPORT_UART_CLK_EN_S);
break;
case 1:
reg_val = reg_val & (~DPORT_UART1_CLK_EN);
reg_val = reg_val | (enable << DPORT_UART1_CLK_EN_S);
break;
default:
abort();
break;
}
WRITE_PERI_REG(DPORT_PERIP_CLK_EN0_REG, reg_val);
}
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
break;
case 1:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*