diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index be7152fa9a..8464783e4f 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -614,7 +614,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf } //set flags for DUAL mode according to output-capability of MOSI and MISO pins. if ((bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) && - (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num))) { + (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num)) && + (bus_config->miso_io_num != bus_config->mosi_io_num)) { temp_flag |= SPICOMMON_BUSFLAG_DUAL; } diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c index 10dcbc9344..688d77022f 100644 --- a/components/esp_driver_spi/src/gpspi/spi_master.c +++ b/components/esp_driver_spi/src/gpspi/spi_master.c @@ -633,9 +633,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz) { - if ((spi_device_t *)handle == NULL || freq_khz == NULL) { - return ESP_ERR_INVALID_ARG; - } + SPI_CHECK(handle && freq_khz, "invalid arg", ESP_ERR_INVALID_ARG); *freq_khz = handle->hal_dev.timing_conf.real_freq / 1000; return ESP_OK; diff --git a/components/esp_driver_spi/src/gpspi/spi_slave.c b/components/esp_driver_spi/src/gpspi/spi_slave.c index 8ac42193bc..e2d7799bf9 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave.c @@ -104,20 +104,26 @@ static inline bool SPI_SLAVE_ISR_ATTR bus_is_iomux(spi_slave_t *host) return host->flags & SPICOMMON_BUSFLAG_IOMUX_PINS; } -static void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host) +static inline void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host) { +#if SPI_LL_SLAVE_NEEDS_CS_WORKAROUND + // This workaround only for ESP32 due to old hardware design, see MR !3207 esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, host->cs_in_signal, false); +#endif } // Use this function instead of cs_initial to avoid overwrite the output config // This is used in test by internal gpio matrix connections static inline void SPI_SLAVE_ISR_ATTR restore_cs(spi_slave_t *host) { +#if SPI_LL_SLAVE_NEEDS_CS_WORKAROUND + // This workaround only for ESP32 due to old hardware design, see MR !3207 if (host->cs_iomux) { gpio_ll_set_input_signal_from(GPIO_HAL_GET_HW(GPIO_PORT_0), host->cs_in_signal, false); } else { esp_rom_gpio_connect_in_signal(host->cfg.spics_io_num, host->cs_in_signal, false); } +#endif } #if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE) @@ -640,21 +646,13 @@ static void SPI_SLAVE_ISR_ATTR s_spi_slave_dma_prepare_data(spi_dma_ctx_t *dma_c spi_dma_reset(dma_ctx->rx_dma_chan); spi_slave_hal_hw_prepare_rx(hal->hw); + spi_dma_start(dma_ctx->rx_dma_chan, dma_ctx->dmadesc_rx); } if (hal->tx_buffer) { spicommon_dma_desc_setup_link(dma_ctx->dmadesc_tx, hal->tx_buffer, (hal->bitlen + 7) / 8, false); spi_dma_reset(dma_ctx->tx_dma_chan); spi_slave_hal_hw_prepare_tx(hal->hw); - } -} - -static void SPI_SLAVE_ISR_ATTR s_spi_slave_start_dma(spi_dma_ctx_t *dma_ctx, spi_slave_hal_context_t *hal) -{ - if (hal->rx_buffer) { - spi_dma_start(dma_ctx->rx_dma_chan, dma_ctx->dmadesc_rx); - } - if (hal->tx_buffer) { spi_dma_start(dma_ctx->tx_dma_chan, dma_ctx->dmadesc_tx); } } @@ -784,10 +782,7 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) //The slave rx dma get disturbed by unexpected transaction. Only connect the CS and start DMA when slave is ready. if (use_dma) { - // Note: order of restore_cs and s_spi_slave_start_dma is important - // restore_cs also bring potential glitch, should happen before start DMA restore_cs(host); - s_spi_slave_start_dma(host->dma_ctx, hal); } //Kick off transfer diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c index 67f094bd62..3ff7588c0b 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -1855,6 +1855,7 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]") spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; buscfg.flags |= SPICOMMON_BUSFLAG_SLP_ALLOW_PD; + buscfg.miso_io_num = buscfg.mosi_io_num; // set spi "self-loop" uint8_t send[16] = "hello spi x\n"; uint8_t recv[16]; spi_transaction_t trans_cfg = { @@ -1871,8 +1872,6 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]") #endif printf("Retention on GPSPI%d with dma: %d\n", periph + 1, use_dma); TEST_ESP_OK(spi_bus_initialize(periph, &buscfg, use_dma)); - // set spi "self-loop" after bus initialized - spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[periph].spid_out); TEST_ESP_OK(spi_bus_add_device(periph, &devcfg, &dev_handle)); for (uint8_t cnt = 0; cnt < 3; cnt ++) { @@ -1927,9 +1926,8 @@ TEST_CASE("test_spi_master_auto_sleep_retention", "[spi]") spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); buscfg.flags = (allow_pd) ? SPICOMMON_BUSFLAG_SLP_ALLOW_PD : 0; buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; + buscfg.miso_io_num = buscfg.mosi_io_num; // set spi "self-loop" TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_DISABLED)); - // set spi "self-loop" after bus initialized - spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); spi_device_handle_t dev_handle; spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index c8cb57dcb9..13ac1afc27 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -44,6 +44,9 @@ extern "C" { #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_MOSI_FREE_LEVEL 0 //Default level after bus initialized +// CS_WORKAROUND: SPI slave with using DMA, the rx dma suffers from unexpected transactions +// before slave is ready, need disconnect CS before and after each transaction +#define SPI_LL_SLAVE_NEEDS_CS_WORKAROUND 1 #define SPI_LL_SLAVE_NEEDS_RESET_WORKAROUND 1 #define SPI_LL_SUPPORT_TIME_TUNING 1 diff --git a/components/hal/esp32p4/include/hal/spi_ll.h b/components/hal/esp32p4/include/hal/spi_ll.h index a1da625f9a..af6c45b85c 100644 --- a/components/hal/esp32p4/include/hal/spi_ll.h +++ b/components/hal/esp32p4/include/hal/spi_ll.h @@ -16,6 +16,7 @@ #include //for abs() #include +#include "hal/config.h" #include "esp_types.h" #include "soc/spi_periph.h" #include "soc/spi_struct.h" @@ -262,6 +263,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->slave.val = 0; hw->user.val = 0; + //Disable unused error_end condition + hw->user1.mst_wfull_err_end_en = 0; + hw->user2.mst_rempty_err_end_en = 0; + hw->dma_conf.val = 0; hw->dma_conf.slv_tx_seg_trans_clr_en = 1; hw->dma_conf.slv_rx_seg_trans_clr_en = 1; @@ -763,13 +768,16 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) *----------------------------------------------------------------------------*/ /** * Set the standard clock mode for master. + * This config take effect only when SPI_CLK (pre-div before periph) div >=2 * * @param hw Beginning address of the peripheral registers. * @param enable_std True for std timing, False for half cycle delay sampling. */ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point) { - //This is not supported +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1); +#endif } /** @@ -777,7 +785,11 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_ */ static inline bool spi_ll_master_is_rx_std_sample_supported(void) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + return true; +#else return false; +#endif } /** diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h deleted file mode 100644 index 1263f22ba5..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h +++ /dev/null @@ -1,1623 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: User-defined control registers */ -/** Type of cmd register - * Command control register - */ -typedef union { - struct { - /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; - * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. - */ - uint32_t conf_bitlen:18; - uint32_t reserved_18:5; - /** update : WT; bitpos: [23]; default: 0; - * Set this bit to synchronize SPI registers from APB clock domain into SPI module - * clock domain, which is only used in SPI master mode. - */ - uint32_t update:1; - /** usr : R/W/SC; bitpos: [24]; default: 0; - * User define command enable. An operation will be triggered when the bit is set. - * The bit will be cleared once the operation done.1: enable 0: disable. Can not be - * changed by CONF_buf. - */ - uint32_t usr:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} spi_cmd_reg_t; - -/** Type of addr register - * Address value register - */ -typedef union { - struct { - /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; - * Address to slave. Can be configured in CONF state. - */ - uint32_t usr_addr_value:32; - }; - uint32_t val; -} spi_addr_reg_t; - -/** Type of user register - * SPI USER control register - */ -typedef union { - struct { - /** doutdin : R/W; bitpos: [0]; default: 0; - * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be - * configured in CONF state. - */ - uint32_t doutdin:1; - uint32_t reserved_1:2; - /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; - * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. - * Can be configured in CONF state. - */ - uint32_t qpi_mode:1; - /** opi_mode : R/W; bitpos: [4]; default: 0; - * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. - * Can be configured in CONF state. - */ - uint32_t opi_mode:1; - /** tsck_i_edge : R/W; bitpos: [5]; default: 0; - * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = - * spi_ck_i. 1:tsck = !spi_ck_i. - */ - uint32_t tsck_i_edge:1; - /** cs_hold : R/W; bitpos: [6]; default: 1; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be - * configured in CONF state. - */ - uint32_t cs_hold:1; - /** cs_setup : R/W; bitpos: [7]; default: 1; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be - * configured in CONF state. - */ - uint32_t cs_setup:1; - /** rsck_i_edge : R/W; bitpos: [8]; default: 0; - * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = - * !spi_ck_i. 1:rsck = spi_ck_i. - */ - uint32_t rsck_i_edge:1; - /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can - * be configured in CONF state. - */ - uint32_t ck_out_edge:1; - uint32_t reserved_10:2; - /** fwrite_dual : R/W; bitpos: [12]; default: 0; - * In the write operations read-data phase apply 2 signals. Can be configured in CONF - * state. - */ - uint32_t fwrite_dual:1; - /** fwrite_quad : R/W; bitpos: [13]; default: 0; - * In the write operations read-data phase apply 4 signals. Can be configured in CONF - * state. - */ - uint32_t fwrite_quad:1; - /** fwrite_oct : R/W; bitpos: [14]; default: 0; - * In the write operations read-data phase apply 8 signals. Can be configured in CONF - * state. - */ - uint32_t fwrite_oct:1; - /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; - * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans - * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is - * not seg-trans mode. Can be configured in CONF state. - */ - uint32_t usr_conf_nxt:1; - uint32_t reserved_16:1; - /** sio : R/W; bitpos: [17]; default: 0; - * Set the bit to enable 3-line half duplex communication mosi and miso signals share - * the same pin. 1: enable 0: disable. Can be configured in CONF state. - */ - uint32_t sio:1; - uint32_t reserved_18:6; - /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: - * disable. Can be configured in CONF state. - */ - uint32_t usr_miso_highpart:1; - /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable - * 0: disable. Can be configured in CONF state. - */ - uint32_t usr_mosi_highpart:1; - /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. Can be configured in - * CONF state. - */ - uint32_t usr_dummy_idle:1; - /** usr_mosi : R/W; bitpos: [27]; default: 0; - * This bit enable the write-data phase of an operation. Can be configured in CONF - * state. - */ - uint32_t usr_mosi:1; - /** usr_miso : R/W; bitpos: [28]; default: 0; - * This bit enable the read-data phase of an operation. Can be configured in CONF - * state. - */ - uint32_t usr_miso:1; - /** usr_dummy : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. Can be configured in CONF state. - */ - uint32_t usr_dummy:1; - /** usr_addr : R/W; bitpos: [30]; default: 0; - * This bit enable the address phase of an operation. Can be configured in CONF state. - */ - uint32_t usr_addr:1; - /** usr_command : R/W; bitpos: [31]; default: 1; - * This bit enable the command phase of an operation. Can be configured in CONF state. - */ - uint32_t usr_command:1; - }; - uint32_t val; -} spi_user_reg_t; - -/** Type of user1 register - * SPI USER control register 1 - */ -typedef union { - struct { - /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; - * The length in spi_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). Can be configured in CONF state. - */ - uint32_t usr_dummy_cyclelen:8; - uint32_t reserved_8:8; - /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; - * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master - * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in - * GP-SPI master FD/HD-mode. - */ - uint32_t mst_wfull_err_end_en:1; - /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; - * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup - * bit. Can be configured in CONF state. - */ - uint32_t cs_setup_time:5; - /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; - * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. - * Can be configured in CONF state. - */ - uint32_t cs_hold_time:5; - /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). Can - * be configured in CONF state. - */ - uint32_t usr_addr_bitlen:5; - }; - uint32_t val; -} spi_user1_reg_t; - -/** Type of user2 register - * SPI USER control register 2 - */ -typedef union { - struct { - /** usr_command_value : R/W; bitpos: [15:0]; default: 0; - * The value of command. Can be configured in CONF state. - */ - uint32_t usr_command_value:16; - uint32_t reserved_16:11; - /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; - * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI - * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error - * is valid in GP-SPI master FD/HD-mode. - */ - uint32_t mst_rempty_err_end_en:1; - /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1). Can - * be configured in CONF state. - */ - uint32_t usr_command_bitlen:4; - }; - uint32_t val; -} spi_user2_reg_t; - - -/** Group: Control and configuration registers */ -/** Type of ctrl register - * SPI control register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** dummy_out : R/W; bitpos: [3]; default: 0; - * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, - * the FSPI bus signals are output. Can be configured in CONF state. - */ - uint32_t dummy_out:1; - uint32_t reserved_4:1; - /** faddr_dual : R/W; bitpos: [5]; default: 0; - * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF - * state. - */ - uint32_t faddr_dual:1; - /** faddr_quad : R/W; bitpos: [6]; default: 0; - * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF - * state. - */ - uint32_t faddr_quad:1; - /** faddr_oct : R/W; bitpos: [7]; default: 0; - * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF - * state. - */ - uint32_t faddr_oct:1; - /** fcmd_dual : R/W; bitpos: [8]; default: 0; - * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF - * state. - */ - uint32_t fcmd_dual:1; - /** fcmd_quad : R/W; bitpos: [9]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF - * state. - */ - uint32_t fcmd_quad:1; - /** fcmd_oct : R/W; bitpos: [10]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF - * state. - */ - uint32_t fcmd_oct:1; - uint32_t reserved_11:3; - /** fread_dual : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can - * be configured in CONF state. - */ - uint32_t fread_dual:1; - /** fread_quad : R/W; bitpos: [15]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can - * be configured in CONF state. - */ - uint32_t fread_quad:1; - /** fread_oct : R/W; bitpos: [16]; default: 0; - * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can - * be configured in CONF state. - */ - uint32_t fread_oct:1; - uint32_t reserved_17:1; - /** q_pol : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in - * CONF state. - */ - uint32_t q_pol:1; - /** d_pol : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in - * CONF state. - */ - uint32_t d_pol:1; - /** hold_pol : R/W; bitpos: [20]; default: 1; - * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be - * configured in CONF state. - */ - uint32_t hold_pol:1; - /** wp_pol : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can - * be configured in CONF state. - */ - uint32_t wp_pol:1; - uint32_t reserved_22:1; - /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; - * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF - * state. - */ - uint32_t rd_bit_order:2; - /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; - * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be - * configured in CONF state. - */ - uint32_t wr_bit_order:2; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_ctrl_reg_t; - -/** Type of ms_dlen register - * SPI data bit length control register - */ -typedef union { - struct { - /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; - * The value of these bits is the configured SPI transmission data bit length in - * master mode DMA controlled transfer or CPU controlled transfer. The value is also - * the configured bit length in slave mode DMA RX controlled transfer. The register - * value shall be (bit_num-1). Can be configured in CONF state. - */ - uint32_t ms_data_bitlen:18; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_ms_dlen_reg_t; - -/** Type of misc register - * SPI misc register - */ -typedef union { - struct { - /** cs0_dis : R/W; bitpos: [0]; default: 0; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can - * be configured in CONF state. - */ - uint32_t cs0_dis:1; - /** cs1_dis : R/W; bitpos: [1]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can - * be configured in CONF state. - */ - uint32_t cs1_dis:1; - /** cs2_dis : R/W; bitpos: [2]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can - * be configured in CONF state. - */ - uint32_t cs2_dis:1; - /** cs3_dis : R/W; bitpos: [3]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can - * be configured in CONF state. - */ - uint32_t cs3_dis:1; - /** cs4_dis : R/W; bitpos: [4]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can - * be configured in CONF state. - */ - uint32_t cs4_dis:1; - /** cs5_dis : R/W; bitpos: [5]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can - * be configured in CONF state. - */ - uint32_t cs5_dis:1; - /** ck_dis : R/W; bitpos: [6]; default: 0; - * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. - */ - uint32_t ck_dis:1; - /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; - * In the master mode the bits are the polarity of spi cs line, the value is - * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - */ - uint32_t master_cs_pol:6; - uint32_t reserved_13:3; - /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0; - * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR - * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. - */ - uint32_t clk_data_dtr_en:1; - /** data_dtr_en : R/W; bitpos: [17]; default: 0; - * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master - * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. - * Can be configured in CONF state. - */ - uint32_t data_dtr_en:1; - /** addr_dtr_en : R/W; bitpos: [18]; default: 0; - * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master - * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be - * configured in CONF state. - */ - uint32_t addr_dtr_en:1; - /** cmd_dtr_en : R/W; bitpos: [19]; default: 0; - * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master - * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be - * configured in CONF state. - */ - uint32_t cmd_dtr_en:1; - uint32_t reserved_20:3; - /** slave_cs_pol : R/W; bitpos: [23]; default: 0; - * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in - * CONF state. - */ - uint32_t slave_cs_pol:1; - /** dqs_idle_edge : R/W; bitpos: [24]; default: 0; - * The default value of spi_dqs. Can be configured in CONF state. - */ - uint32_t dqs_idle_edge:1; - uint32_t reserved_25:4; - /** ck_idle_edge : R/W; bitpos: [29]; default: 0; - * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be - * configured in CONF state. - */ - uint32_t ck_idle_edge:1; - /** cs_keep_active : R/W; bitpos: [30]; default: 0; - * spi cs line keep low when the bit is set. Can be configured in CONF state. - */ - uint32_t cs_keep_active:1; - /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; - * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: - * spi quad input swap disable. Can be configured in CONF state. - */ - uint32_t quad_din_pin_swap:1; - }; - uint32_t val; -} spi_misc_reg_t; - -/** Type of dma_conf register - * SPI DMA control register - */ -typedef union { - struct { - /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; - * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: - * DMA TX FIFO is ready for sending data. - */ - uint32_t dma_outfifo_empty:1; - /** dma_infifo_full : RO; bitpos: [1]; default: 1; - * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. - * 0: DMA RX FIFO is ready for receiving data. - */ - uint32_t dma_infifo_full:1; - uint32_t reserved_2:16; - /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; - * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. - */ - uint32_t dma_slv_seg_trans_en:1; - /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; - * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: - * spi_dma_infifo_full_vld is cleared by spi_trans_done. - */ - uint32_t slv_rx_seg_trans_clr_en:1; - /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; - * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: - * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. - */ - uint32_t slv_tx_seg_trans_clr_en:1; - /** rx_eof_en : R/W; bitpos: [21]; default: 0; - * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to - * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: - * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or - * spi_dma_seg_trans_done in seg-trans. - */ - uint32_t rx_eof_en:1; - uint32_t reserved_22:5; - /** dma_rx_ena : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI DMA controlled receive data mode. - */ - uint32_t dma_rx_ena:1; - /** dma_tx_ena : R/W; bitpos: [28]; default: 0; - * Set this bit to enable SPI DMA controlled send data mode. - */ - uint32_t dma_tx_ena:1; - /** rx_afifo_rst : WT; bitpos: [29]; default: 0; - * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and - * slave mode transfer. - */ - uint32_t rx_afifo_rst:1; - /** buf_afifo_rst : WT; bitpos: [30]; default: 0; - * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU - * controlled mode transfer and master mode transfer. - */ - uint32_t buf_afifo_rst:1; - /** dma_afifo_rst : WT; bitpos: [31]; default: 0; - * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA - * controlled mode transfer. - */ - uint32_t dma_afifo_rst:1; - }; - uint32_t val; -} spi_dma_conf_reg_t; - -/** Type of slave register - * SPI slave control register - */ -typedef union { - struct { - /** clk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. Can be configured in CONF state. - */ - uint32_t clk_mode:2; - /** clk_mode_13 : R/W; bitpos: [2]; default: 0; - * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: - * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. - */ - uint32_t clk_mode_13:1; - /** rsck_data_out : R/W; bitpos: [3]; default: 0; - * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge - * 0: output data at tsck posedge - */ - uint32_t rsck_data_out:1; - uint32_t reserved_4:4; - /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in - * DMA controlled mode(Rd_DMA). 0: others - */ - uint32_t slv_rddma_bitlen_en:1; - /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length - * in DMA controlled mode(Wr_DMA). 0: others - */ - uint32_t slv_wrdma_bitlen_en:1; - /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in - * CPU controlled mode(Rd_BUF). 0: others - */ - uint32_t slv_rdbuf_bitlen_en:1; - /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length - * in CPU controlled mode(Wr_BUF). 0: others - */ - uint32_t slv_wrbuf_bitlen_en:1; - /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; - * Represents the effective bit of the last received data byte in SPI slave FD and HD - * mode. - */ - uint32_t slv_last_byte_strb:8; - uint32_t reserved_20:2; - /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; - * The magic value of BM table in master DMA seg-trans. - */ - uint32_t dma_seg_magic_value:4; - /** slave_mode : R/W; bitpos: [26]; default: 0; - * Set SPI work mode. 1: slave mode 0: master mode. - */ - uint32_t slave_mode:1; - /** soft_reset : WT; bitpos: [27]; default: 0; - * Software reset enable, reset the spi clock line cs line and data lines. Can be - * configured in CONF state. - */ - uint32_t soft_reset:1; - /** usr_conf : R/W; bitpos: [28]; default: 0; - * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans - * will start. 0: This is not seg-trans mode. - */ - uint32_t usr_conf:1; - /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; - * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before - * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI - * transfer. - */ - uint32_t mst_fd_wait_dma_tx_data:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_slave_reg_t; - -/** Type of slave1 register - * SPI slave control register 1 - */ -typedef union { - struct { - /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; - * The transferred data bit length in SPI slave FD and HD mode. - */ - uint32_t slv_data_bitlen:18; - /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; - * In the slave mode it is the value of command. - */ - uint32_t slv_last_command:8; - /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; - * In the slave mode it is the value of address. - */ - uint32_t slv_last_addr:6; - }; - uint32_t val; -} spi_slave1_reg_t; - - -/** Group: Clock control registers */ -/** Type of clock register - * SPI clock control register - */ -typedef union { - struct { - /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; - * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be - * 0. Can be configured in CONF state. - */ - uint32_t clkcnt_l:6; - /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; - * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it - * must be 0. Can be configured in CONF state. - */ - uint32_t clkcnt_h:6; - /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; - * In the master mode it is the divider of spi_clk. So spi_clk frequency is - * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. - */ - uint32_t clkcnt_n:6; - /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; - * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. - */ - uint32_t clkdiv_pre:4; - uint32_t reserved_22:8; - /** clk_edge_sel : R/W; bitpos: [30]; default: 0; - * Configures use standard clock sampling edge or delay the sampling edge by half a - * cycle in master transfer. - * 0: clock sampling edge is delayed by half a cycle. - * 1: clock sampling edge is standard. - * Can be configured in CONF state. - */ - uint32_t clk_edge_sel:1; - /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system - * clock. Can be configured in CONF state. - */ - uint32_t clk_equ_sysclk:1; - }; - uint32_t val; -} spi_clock_reg_t; - -/** Type of clk_gate register - * SPI module clock and register clock control - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Set this bit to enable clk gate - */ - uint32_t clk_en:1; - /** mst_clk_active : R/W; bitpos: [1]; default: 0; - * Set this bit to power on the SPI module clock. - */ - uint32_t mst_clk_active:1; - /** mst_clk_sel : R/W; bitpos: [2]; default: 0; - * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. - * 0: XTAL CLK. - */ - uint32_t mst_clk_sel:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_clk_gate_reg_t; - - -/** Group: Timing registers */ -/** Type of din_mode register - * SPI input delay mode configuration - */ -typedef union { - struct { - /** din0_mode : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din0_mode:2; - /** din1_mode : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din1_mode:2; - /** din2_mode : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din2_mode:2; - /** din3_mode : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din3_mode:2; - /** din4_mode : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din4_mode:2; - /** din5_mode : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din5_mode:2; - /** din6_mode : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din6_mode:2; - /** din7_mode : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input without delayed, - * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk. Can be configured in CONF state. - */ - uint32_t din7_mode:2; - /** timing_hclk_active : R/W; bitpos: [16]; default: 0; - * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF - * state. - */ - uint32_t timing_hclk_active:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_din_mode_reg_t; - -/** Type of din_num register - * SPI input delay number configuration - */ -typedef union { - struct { - /** din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din0_num:2; - /** din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din1_num:2; - /** din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din2_num:2; - /** din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din3_num:2; - /** din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din4_num:2; - /** din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din5_num:2; - /** din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din6_num:2; - /** din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... Can be configured in CONF state. - */ - uint32_t din7_num:2; - uint32_t reserved_16:16; - }; - uint32_t val; -} spi_din_num_reg_t; - -/** Type of dout_mode register - * SPI output delay mode configuration - */ -typedef union { - struct { - /** dout0_mode : R/W; bitpos: [0]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout0_mode:1; - /** dout1_mode : R/W; bitpos: [1]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout1_mode:1; - /** dout2_mode : R/W; bitpos: [2]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout2_mode:1; - /** dout3_mode : R/W; bitpos: [3]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout3_mode:1; - /** dout4_mode : R/W; bitpos: [4]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout4_mode:1; - /** dout5_mode : R/W; bitpos: [5]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout5_mode:1; - /** dout6_mode : R/W; bitpos: [6]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout6_mode:1; - /** dout7_mode : R/W; bitpos: [7]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output without delayed, - * 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t dout7_mode:1; - /** d_dqs_mode : R/W; bitpos: [8]; default: 0; - * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without - * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be - * configured in CONF state. - */ - uint32_t d_dqs_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_dout_mode_reg_t; - - -/** Group: Interrupt registers */ -/** Type of dma_int_ena register - * SPI interrupt enable register - */ -typedef union { - struct { - /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; - * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - uint32_t dma_infifo_full_err_int_ena:1; - /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; - * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - uint32_t dma_outfifo_empty_err_int_ena:1; - /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; - * The enable bit for SPI slave Ex_QPI interrupt. - */ - uint32_t slv_ex_qpi_int_ena:1; - /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI slave En_QPI interrupt. - */ - uint32_t slv_en_qpi_int_ena:1; - /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI slave CMD7 interrupt. - */ - uint32_t slv_cmd7_int_ena:1; - /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI slave CMD8 interrupt. - */ - uint32_t slv_cmd8_int_ena:1; - /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI slave CMD9 interrupt. - */ - uint32_t slv_cmd9_int_ena:1; - /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI slave CMDA interrupt. - */ - uint32_t slv_cmda_int_ena:1; - /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - uint32_t slv_rd_dma_done_int_ena:1; - /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - uint32_t slv_wr_dma_done_int_ena:1; - /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; - * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - uint32_t slv_rd_buf_done_int_ena:1; - /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; - * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - uint32_t slv_wr_buf_done_int_ena:1; - /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; - * The enable bit for SPI_TRANS_DONE_INT interrupt. - */ - uint32_t trans_done_int_ena:1; - /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; - * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - uint32_t dma_seg_trans_done_int_ena:1; - /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; - * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - uint32_t seg_magic_err_int_ena:1; - /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; - * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - uint32_t slv_buf_addr_err_int_ena:1; - /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; - * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - uint32_t slv_cmd_err_int_ena:1; - /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; - * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - uint32_t mst_rx_afifo_wfull_err_int_ena:1; - /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; - * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - uint32_t mst_tx_afifo_rempty_err_int_ena:1; - /** app2_int_ena : R/W; bitpos: [19]; default: 0; - * The enable bit for SPI_APP2_INT interrupt. - */ - uint32_t app2_int_ena:1; - /** app1_int_ena : R/W; bitpos: [20]; default: 0; - * The enable bit for SPI_APP1_INT interrupt. - */ - uint32_t app1_int_ena:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_dma_int_ena_reg_t; - -/** Type of dma_int_clr register - * SPI interrupt clear register - */ -typedef union { - struct { - /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; - * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - uint32_t dma_infifo_full_err_int_clr:1; - /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; - * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - uint32_t dma_outfifo_empty_err_int_clr:1; - /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; - * The clear bit for SPI slave Ex_QPI interrupt. - */ - uint32_t slv_ex_qpi_int_clr:1; - /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for SPI slave En_QPI interrupt. - */ - uint32_t slv_en_qpi_int_clr:1; - /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for SPI slave CMD7 interrupt. - */ - uint32_t slv_cmd7_int_clr:1; - /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for SPI slave CMD8 interrupt. - */ - uint32_t slv_cmd8_int_clr:1; - /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for SPI slave CMD9 interrupt. - */ - uint32_t slv_cmd9_int_clr:1; - /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for SPI slave CMDA interrupt. - */ - uint32_t slv_cmda_int_clr:1; - /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - uint32_t slv_rd_dma_done_int_clr:1; - /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - uint32_t slv_wr_dma_done_int_clr:1; - /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; - * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - uint32_t slv_rd_buf_done_int_clr:1; - /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; - * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - uint32_t slv_wr_buf_done_int_clr:1; - /** trans_done_int_clr : WT; bitpos: [12]; default: 0; - * The clear bit for SPI_TRANS_DONE_INT interrupt. - */ - uint32_t trans_done_int_clr:1; - /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; - * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - uint32_t dma_seg_trans_done_int_clr:1; - /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; - * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - uint32_t seg_magic_err_int_clr:1; - /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; - * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - uint32_t slv_buf_addr_err_int_clr:1; - /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; - * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - uint32_t slv_cmd_err_int_clr:1; - /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; - * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - uint32_t mst_rx_afifo_wfull_err_int_clr:1; - /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; - * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - uint32_t mst_tx_afifo_rempty_err_int_clr:1; - /** app2_int_clr : WT; bitpos: [19]; default: 0; - * The clear bit for SPI_APP2_INT interrupt. - */ - uint32_t app2_int_clr:1; - /** app1_int_clr : WT; bitpos: [20]; default: 0; - * The clear bit for SPI_APP1_INT interrupt. - */ - uint32_t app1_int_clr:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_dma_int_clr_reg_t; - -/** Type of dma_int_raw register - * SPI interrupt raw register - */ -typedef union { - struct { - /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the - * receive data. 0: Others. - */ - uint32_t dma_infifo_full_err_int_raw:1; - /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in - * master mode and send out all 0 in slave mode. 0: Others. - */ - uint32_t dma_outfifo_empty_err_int_raw:1; - /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission - * is ended. 0: Others. - */ - uint32_t slv_ex_qpi_int_raw:1; - /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission - * is ended. 0: Others. - */ - uint32_t slv_en_qpi_int_raw:1; - /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is - * ended. 0: Others. - */ - uint32_t slv_cmd7_int_raw:1; - /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is - * ended. 0: Others. - */ - uint32_t slv_cmd8_int_raw:1; - /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is - * ended. 0: Others. - */ - uint32_t slv_cmd9_int_raw:1; - /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is - * ended. 0: Others. - */ - uint32_t slv_cmda_int_raw:1; - /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA - * transmission is ended. 0: Others. - */ - uint32_t slv_rd_dma_done_int_raw:1; - /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA - * transmission is ended. 0: Others. - */ - uint32_t slv_wr_dma_done_int_raw:1; - /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF - * transmission is ended. 0: Others. - */ - uint32_t slv_rd_buf_done_int_raw:1; - /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF - * transmission is ended. 0: Others. - */ - uint32_t slv_wr_buf_done_int_raw:1; - /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is - * ended. 0: others. - */ - uint32_t trans_done_int_raw:1; - /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA - * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. - * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans - * is not ended or not occurred. - */ - uint32_t dma_seg_trans_done_int_raw:1; - /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer - * is error in the DMA seg-conf-trans. 0: others. - */ - uint32_t seg_magic_err_int_raw:1; - /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address - * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is - * bigger than 63. 0: Others. - */ - uint32_t slv_buf_addr_err_int_raw:1; - /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the - * current SPI slave HD mode transmission is not supported. 0: Others. - */ - uint32_t slv_cmd_err_int_raw:1; - /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO - * write-full error when SPI inputs data in master mode. 0: Others. - */ - uint32_t mst_rx_afifo_wfull_err_int_raw:1; - /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF - * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. - */ - uint32_t mst_tx_afifo_rempty_err_int_raw:1; - /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. - */ - uint32_t app2_int_raw:1; - /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. - */ - uint32_t app1_int_raw:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_dma_int_raw_reg_t; - -/** Type of dma_int_st register - * SPI interrupt status register - */ -typedef union { - struct { - /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; - * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - uint32_t dma_infifo_full_err_int_st:1; - /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; - * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - uint32_t dma_outfifo_empty_err_int_st:1; - /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; - * The status bit for SPI slave Ex_QPI interrupt. - */ - uint32_t slv_ex_qpi_int_st:1; - /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; - * The status bit for SPI slave En_QPI interrupt. - */ - uint32_t slv_en_qpi_int_st:1; - /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; - * The status bit for SPI slave CMD7 interrupt. - */ - uint32_t slv_cmd7_int_st:1; - /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; - * The status bit for SPI slave CMD8 interrupt. - */ - uint32_t slv_cmd8_int_st:1; - /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; - * The status bit for SPI slave CMD9 interrupt. - */ - uint32_t slv_cmd9_int_st:1; - /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; - * The status bit for SPI slave CMDA interrupt. - */ - uint32_t slv_cmda_int_st:1; - /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; - * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - uint32_t slv_rd_dma_done_int_st:1; - /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; - * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - uint32_t slv_wr_dma_done_int_st:1; - /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; - * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - uint32_t slv_rd_buf_done_int_st:1; - /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; - * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - uint32_t slv_wr_buf_done_int_st:1; - /** trans_done_int_st : RO; bitpos: [12]; default: 0; - * The status bit for SPI_TRANS_DONE_INT interrupt. - */ - uint32_t trans_done_int_st:1; - /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; - * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - uint32_t dma_seg_trans_done_int_st:1; - /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; - * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - uint32_t seg_magic_err_int_st:1; - /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; - * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - uint32_t slv_buf_addr_err_int_st:1; - /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; - * The status bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - uint32_t slv_cmd_err_int_st:1; - /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; - * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - uint32_t mst_rx_afifo_wfull_err_int_st:1; - /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; - * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - uint32_t mst_tx_afifo_rempty_err_int_st:1; - /** app2_int_st : RO; bitpos: [19]; default: 0; - * The status bit for SPI_APP2_INT interrupt. - */ - uint32_t app2_int_st:1; - /** app1_int_st : RO; bitpos: [20]; default: 0; - * The status bit for SPI_APP1_INT interrupt. - */ - uint32_t app1_int_st:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_dma_int_st_reg_t; - -/** Type of dma_int_set register - * SPI interrupt software set register - */ -typedef union { - struct { - /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; - * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - uint32_t dma_infifo_full_err_int_set:1; - /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; - * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - uint32_t dma_outfifo_empty_err_int_set:1; - /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; - * The software set bit for SPI slave Ex_QPI interrupt. - */ - uint32_t slv_ex_qpi_int_set:1; - /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; - * The software set bit for SPI slave En_QPI interrupt. - */ - uint32_t slv_en_qpi_int_set:1; - /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; - * The software set bit for SPI slave CMD7 interrupt. - */ - uint32_t slv_cmd7_int_set:1; - /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; - * The software set bit for SPI slave CMD8 interrupt. - */ - uint32_t slv_cmd8_int_set:1; - /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; - * The software set bit for SPI slave CMD9 interrupt. - */ - uint32_t slv_cmd9_int_set:1; - /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; - * The software set bit for SPI slave CMDA interrupt. - */ - uint32_t slv_cmda_int_set:1; - /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; - * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - uint32_t slv_rd_dma_done_int_set:1; - /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; - * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - uint32_t slv_wr_dma_done_int_set:1; - /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; - * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - uint32_t slv_rd_buf_done_int_set:1; - /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; - * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - uint32_t slv_wr_buf_done_int_set:1; - /** trans_done_int_set : WT; bitpos: [12]; default: 0; - * The software set bit for SPI_TRANS_DONE_INT interrupt. - */ - uint32_t trans_done_int_set:1; - /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; - * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - uint32_t dma_seg_trans_done_int_set:1; - /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; - * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - uint32_t seg_magic_err_int_set:1; - /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; - * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - uint32_t slv_buf_addr_err_int_set:1; - /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; - * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - uint32_t slv_cmd_err_int_set:1; - /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; - * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - uint32_t mst_rx_afifo_wfull_err_int_set:1; - /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; - * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - uint32_t mst_tx_afifo_rempty_err_int_set:1; - /** app2_int_set : WT; bitpos: [19]; default: 0; - * The software set bit for SPI_APP2_INT interrupt. - */ - uint32_t app2_int_set:1; - /** app1_int_set : WT; bitpos: [20]; default: 0; - * The software set bit for SPI_APP1_INT interrupt. - */ - uint32_t app1_int_set:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_dma_int_set_reg_t; - - -/** Group: CPU-controlled data buffer */ -/** Type of w0 register - * SPI CPU-controlled buffer0 - */ -typedef union { - struct { - /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf0:32; - }; - uint32_t val; -} spi_w0_reg_t; - -/** Type of w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_w1_reg_t; - -/** Type of w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_w2_reg_t; - -/** Type of w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_w3_reg_t; - -/** Type of w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_w4_reg_t; - -/** Type of w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_w5_reg_t; - -/** Type of w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_w6_reg_t; - -/** Type of w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_w7_reg_t; - -/** Type of w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_w8_reg_t; - -/** Type of w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_w9_reg_t; - -/** Type of w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_w10_reg_t; - -/** Type of w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_w11_reg_t; - -/** Type of w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_w12_reg_t; - -/** Type of w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_w13_reg_t; - -/** Type of w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_w14_reg_t; - -/** Type of w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_w15_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 37761424; - * SPI register version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_date_reg_t; - - -typedef struct { - volatile spi_cmd_reg_t cmd; - volatile spi_addr_reg_t addr; - volatile spi_ctrl_reg_t ctrl; - volatile spi_clock_reg_t clock; - volatile spi_user_reg_t user; - volatile spi_user1_reg_t user1; - volatile spi_user2_reg_t user2; - volatile spi_ms_dlen_reg_t ms_dlen; - volatile spi_misc_reg_t misc; - volatile spi_din_mode_reg_t din_mode; - volatile spi_din_num_reg_t din_num; - volatile spi_dout_mode_reg_t dout_mode; - volatile spi_dma_conf_reg_t dma_conf; - volatile spi_dma_int_ena_reg_t dma_int_ena; - volatile spi_dma_int_clr_reg_t dma_int_clr; - volatile spi_dma_int_raw_reg_t dma_int_raw; - volatile spi_dma_int_st_reg_t dma_int_st; - volatile spi_dma_int_set_reg_t dma_int_set; - uint32_t reserved_048[20]; - volatile spi_w0_reg_t w0; - volatile spi_w1_reg_t w1; - volatile spi_w2_reg_t w2; - volatile spi_w3_reg_t w3; - volatile spi_w4_reg_t w4; - volatile spi_w5_reg_t w5; - volatile spi_w6_reg_t w6; - volatile spi_w7_reg_t w7; - volatile spi_w8_reg_t w8; - volatile spi_w9_reg_t w9; - volatile spi_w10_reg_t w10; - volatile spi_w11_reg_t w11; - volatile spi_w12_reg_t w12; - volatile spi_w13_reg_t w13; - volatile spi_w14_reg_t w14; - volatile spi_w15_reg_t w15; - uint32_t reserved_0d8[2]; - volatile spi_slave_reg_t slave; - volatile spi_slave1_reg_t slave1; - volatile spi_clk_gate_reg_t clk_gate; - uint32_t reserved_0ec; - volatile spi_date_reg_t date; -} spi_dev_t; - -extern spi_dev_t GPSPI2; - -#ifndef __cplusplus -_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h index 64da6d07f3..99be51bc31 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h @@ -627,7 +627,15 @@ typedef union { * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. */ uint32_t clkdiv_pre:4; - uint32_t reserved_22:9; + uint32_t reserved_22:8; + /** clk_edge_sel : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ + uint32_t clk_edge_sel:1; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. @@ -975,7 +983,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 35680770; + /** date : R/W; bitpos: [27:0]; default: 37761424; * SPI register version. */ uint32_t date:28; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h deleted file mode 100644 index 429a1a7145..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h +++ /dev/null @@ -1,799 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of mode register - * TWAI mode register. - */ -typedef union { - struct { - /** reset_mode : R/W; bitpos: [0]; default: 1; - * 1: reset, detection of a set reset mode bit results in aborting the current - * transmission/reception of a message and entering the reset mode. 0: normal, on the - * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the - * operating mode. - */ - uint32_t reset_mode:1; - /** listen_only_mode : R/W; bitpos: [1]; default: 0; - * 1: listen only, in this mode the TWAI controller would give no acknowledge to the - * TWAI-bus, even if a message is received successfully. The error counters are - * stopped at the current value. 0: normal. - */ - uint32_t listen_only_mode:1; - /** self_test_mode : R/W; bitpos: [2]; default: 0; - * 1: self test, in this mode a full node test is possible without any other active - * node on the bus using the self reception request command. The TWAI controller will - * perform a successful transmission, even if there is no acknowledge received. 0: - * normal, an acknowledge is required for successful transmission. - */ - uint32_t self_test_mode:1; - /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; - * 1:single, the single acceptance filter option is enabled (one filter with the - * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled - * (two filters, each with the length of 16 bit are active). - */ - uint32_t acceptance_filter_mode:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} twai_mode_reg_t; - -/** Type of cmd register - * TWAI command register. - */ -typedef union { - struct { - /** tx_request : WO; bitpos: [0]; default: 0; - * 1: present, a message shall be transmitted. 0: absent - */ - uint32_t tx_request:1; - /** abort_tx : WO; bitpos: [1]; default: 0; - * 1: present, if not already in progress, a pending transmission request is - * cancelled. 0: absent - */ - uint32_t abort_tx:1; - /** release_buffer : WO; bitpos: [2]; default: 0; - * 1: released, the receive buffer, representing the message memory space in the - * RXFIFO is released. 0: no action - */ - uint32_t release_buffer:1; - /** clear_data_overrun : WO; bitpos: [3]; default: 0; - * 1: clear, the data overrun status bit is cleared. 0: no action. - */ - uint32_t clear_data_overrun:1; - /** self_rx_request : WO; bitpos: [4]; default: 0; - * 1: present, a message shall be transmitted and received simultaneously. 0: absent. - */ - uint32_t self_rx_request:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} twai_cmd_reg_t; - -/** Type of bus_timing_0 register - * Bit timing configuration register 0. - */ -typedef union { - struct { - /** baud_presc : R/W; bitpos: [13:0]; default: 0; - * The period of the TWAI system clock is programmable and determines the individual - * bit timing. Software has R/W permission in reset mode and RO permission in - * operation mode. - */ - uint32_t baud_presc:14; - /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; - * The synchronization jump width defines the maximum number of clock cycles a bit - * period may be shortened or lengthened. Software has R/W permission in reset mode - * and RO in operation mode. - */ - uint32_t sync_jump_width:2; - uint32_t reserved_16:16; - }; - uint32_t val; -} twai_bus_timing_0_reg_t; - -/** Type of bus_timing_1 register - * Bit timing configuration register 1. - */ -typedef union { - struct { - /** time_segment1 : R/W; bitpos: [3:0]; default: 0; - * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in - * reset mode and RO in operation mode. - */ - uint32_t time_segment1:4; - /** time_segment2 : R/W; bitpos: [6:4]; default: 0; - * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in - * reset mode and RO in operation mode. - */ - uint32_t time_segment2:3; - /** time_sampling : R/W; bitpos: [7]; default: 0; - * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. - * Software has R/W permission in reset mode and RO in operation mode. - */ - uint32_t time_sampling:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_bus_timing_1_reg_t; - -/** Type of err_warning_limit register - * TWAI error threshold configuration register. - */ -typedef union { - struct { - /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; - * The threshold that trigger error warning interrupt when this interrupt is enabled. - * Software has R/W permission in reset mode and RO in operation mode. - */ - uint32_t err_warning_limit:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_err_warning_limit_reg_t; - -/** Type of clock_divider register - * Clock divider register. - */ -typedef union { - struct { - /** cd : R/W; bitpos: [7:0]; default: 0; - * These bits are used to define the frequency at the external CLKOUT pin. - */ - uint32_t cd:8; - /** clock_off : R/W; bitpos: [8]; default: 0; - * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has - * R/W permission in reset mode and RO in operation mode. - */ - uint32_t clock_off:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} twai_clock_divider_reg_t; - -/** Type of sw_standby_cfg register - * Software configure standby pin directly. - */ -typedef union { - struct { - /** sw_standby_en : R/W; bitpos: [0]; default: 0; - * Enable standby pin. - */ - uint32_t sw_standby_en:1; - /** sw_standby_clr : R/W; bitpos: [1]; default: 1; - * Clear standby pin. - */ - uint32_t sw_standby_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} twai_sw_standby_cfg_reg_t; - -/** Type of hw_cfg register - * Hardware configure standby pin. - */ -typedef union { - struct { - /** hw_standby_en : R/W; bitpos: [0]; default: 0; - * Enable function that hardware control standby pin. - */ - uint32_t hw_standby_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} twai_hw_cfg_reg_t; - -/** Type of hw_standby_cnt register - * Configure standby counter. - */ -typedef union { - struct { - /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; - * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN - * is enabled. - */ - uint32_t standby_wait_cnt:32; - }; - uint32_t val; -} twai_hw_standby_cnt_reg_t; - -/** Type of idle_intr_cnt register - * Configure idle interrupt counter. - */ -typedef union { - struct { - /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; - * Configure the number of cycles before triggering idle interrupt. - */ - uint32_t idle_intr_cnt:32; - }; - uint32_t val; -} twai_idle_intr_cnt_reg_t; - -/** Type of eco_cfg register - * ECO configuration register. - */ -typedef union { - struct { - /** rdn_ena : R/W; bitpos: [0]; default: 0; - * Enable eco module. - */ - uint32_t rdn_ena:1; - /** rdn_result : RO; bitpos: [1]; default: 1; - * Output of eco module. - */ - uint32_t rdn_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} twai_eco_cfg_reg_t; - - -/** Group: Status Registers */ -/** Type of status register - * TWAI status register. - */ -typedef union { - struct { - /** status_receive_buffer : RO; bitpos: [0]; default: 0; - * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no - * message is available - */ - uint32_t status_receive_buffer:1; - /** status_overrun : RO; bitpos: [1]; default: 0; - * 1: overrun, a message was lost because there was not enough space for that message - * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data - * overrun command was given - */ - uint32_t status_overrun:1; - /** status_transmit_buffer : RO; bitpos: [2]; default: 0; - * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the - * CPU cannot access the transmit buffer, a message is either waiting for transmission - * or is in the process of being transmitted - */ - uint32_t status_transmit_buffer:1; - /** status_transmission_complete : RO; bitpos: [3]; default: 0; - * 1: complete, last requested transmission has been successfully completed. 0: - * incomplete, previously requested transmission is not yet completed - */ - uint32_t status_transmission_complete:1; - /** status_receive : RO; bitpos: [4]; default: 0; - * 1: receive, the TWAI controller is receiving a message. 0: idle - */ - uint32_t status_receive:1; - /** status_transmit : RO; bitpos: [5]; default: 0; - * 1: transmit, the TWAI controller is transmitting a message. 0: idle - */ - uint32_t status_transmit:1; - /** status_err : RO; bitpos: [6]; default: 0; - * 1: error, at least one of the error counters has reached or exceeded the CPU - * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error - * counters are below the warning limit - */ - uint32_t status_err:1; - /** status_node_bus_off : RO; bitpos: [7]; default: 0; - * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the - * TWAI controller is involved in bus activities - */ - uint32_t status_node_bus_off:1; - /** status_miss : RO; bitpos: [8]; default: 0; - * 1: current message is destroyed because of FIFO overflow. - */ - uint32_t status_miss:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} twai_status_reg_t; - -/** Type of arb_lost_cap register - * TWAI arbiter lost capture register. - */ -typedef union { - struct { - /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; - * This register contains information about the bit position of losing arbitration. - */ - uint32_t arbitration_lost_capture:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} twai_arb_lost_cap_reg_t; - -/** Type of err_code_cap register - * TWAI error info capture register. - */ -typedef union { - struct { - /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; - * This register contains information about the location of errors on the bus. - */ - uint32_t err_capture_code_segment:5; - /** err_capture_code_direction : RO; bitpos: [5]; default: 0; - * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. - */ - uint32_t err_capture_code_direction:1; - /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; - * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. - */ - uint32_t err_capture_code_type:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_err_code_cap_reg_t; - -/** Type of rx_err_cnt register - * Rx error counter register. - */ -typedef union { - struct { - /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; - * The RX error counter register reflects the current value of the transmit error - * counter. Software has R/W permission in reset mode and RO in operation mode. - */ - uint32_t rx_err_cnt:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_rx_err_cnt_reg_t; - -/** Type of tx_err_cnt register - * Tx error counter register. - */ -typedef union { - struct { - /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; - * The TX error counter register reflects the current value of the transmit error - * counter. Software has R/W permission in reset mode and RO in operation mode. - */ - uint32_t tx_err_cnt:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_tx_err_cnt_reg_t; - -/** Type of rx_message_counter register - * Received message counter register. - */ -typedef union { - struct { - /** rx_message_counter : RO; bitpos: [6:0]; default: 0; - * Reflects the number of messages available within the RXFIFO. The value is - * incremented with each receive event and decremented by the release receive buffer - * command. - */ - uint32_t rx_message_counter:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} twai_rx_message_counter_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of interrupt register - * Interrupt signals' register. - */ -typedef union { - struct { - /** receive_int_st : RO; bitpos: [0]; default: 0; - * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set - * within the interrupt enable register. 0: reset - */ - uint32_t receive_int_st:1; - /** transmit_int_st : RO; bitpos: [1]; default: 0; - * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' - * (released) and the TIE bit is set within the interrupt enable register. 0: reset - */ - uint32_t transmit_int_st:1; - /** err_warning_int_st : RO; bitpos: [2]; default: 0; - * 1: this bit is set on every change (set and clear) of either the error status or - * bus status bits and the EIE bit is set within the interrupt enable register. 0: - * reset - */ - uint32_t err_warning_int_st:1; - /** data_overrun_int_st : RO; bitpos: [3]; default: 0; - * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the - * DOIE bit is set within the interrupt enable register. 0: reset - */ - uint32_t data_overrun_int_st:1; - /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0; - * 1: this bit is set then the timestamp counter reaches the maximum value and - * overflow. - */ - uint32_t ts_counter_ovfl_int_st:1; - /** err_passive_int_st : RO; bitpos: [5]; default: 0; - * 1: this bit is set whenever the TWAI controller has reached the error passive - * status (at least one error counter exceeds the protocol-defined level of 127) or if - * the TWAI controller is in the error passive status and enters the error active - * status again and the EPIE bit is set within the interrupt enable register. 0: reset - */ - uint32_t err_passive_int_st:1; - /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; - * 1: this bit is set when the TWAI controller lost the arbitration and becomes a - * receiver and the ALIE bit is set within the interrupt enable register. 0: reset - */ - uint32_t arbitration_lost_int_st:1; - /** bus_err_int_st : RO; bitpos: [7]; default: 0; - * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and - * the BEIE bit is set within the interrupt enable register. 0: reset - */ - uint32_t bus_err_int_st:1; - /** idle_int_st : RO; bitpos: [8]; default: 0; - * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and - * this interrupt enable bit is set within the interrupt enable register. 0: reset - */ - uint32_t idle_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} twai_interrupt_reg_t; - -/** Type of interrupt_enable register - * Interrupt enable register. - */ -typedef union { - struct { - /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; - * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests - * the respective interrupt. 0: disable - */ - uint32_t ext_receive_int_ena:1; - /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; - * 1: enabled, when a message has been successfully transmitted or the transmit buffer - * is accessible again (e.g. after an abort transmission command), the TWAI controller - * requests the respective interrupt. 0: disable - */ - uint32_t ext_transmit_int_ena:1; - /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; - * 1: enabled, if the error or bus status change (see status register. Table 14), the - * TWAI controllerrequests the respective interrupt. 0: disable - */ - uint32_t ext_err_warning_int_ena:1; - /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; - * 1: enabled, if the data overrun status bit is set (see status register. Table 14), - * the TWAI controllerrequests the respective interrupt. 0: disable - */ - uint32_t ext_data_overrun_int_ena:1; - /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0; - * enable the timestamp counter overflow interrupt request. - */ - uint32_t ts_counter_ovfl_int_ena:1; - /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; - * 1: enabled, if the error status of the TWAI controller changes from error active to - * error passive or vice versa, the respective interrupt is requested. 0: disable - */ - uint32_t err_passive_int_ena:1; - /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; - * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt - * is requested. 0: disable - */ - uint32_t arbitration_lost_int_ena:1; - /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; - * 1: enabled, if an bus error has been detected, the TWAI controller requests the - * respective interrupt. 0: disable - */ - uint32_t bus_err_int_ena:1; - /** idle_int_ena : RO; bitpos: [8]; default: 0; - * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the - * respective interrupt. 0: disable - */ - uint32_t idle_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} twai_interrupt_enable_reg_t; - - -/** Group: Data Registers */ -/** Type of data_0 register - * Data register 0. - */ -typedef union { - struct { - /** data_0 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 0 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 0 and when - * software initiate read operation, it is rx data register 0. - */ - uint32_t data_0:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_0_reg_t; - -/** Type of data_1 register - * Data register 1. - */ -typedef union { - struct { - /** data_1 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 1 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 1 and when - * software initiate read operation, it is rx data register 1. - */ - uint32_t data_1:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_1_reg_t; - -/** Type of data_2 register - * Data register 2. - */ -typedef union { - struct { - /** data_2 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 2 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 2 and when - * software initiate read operation, it is rx data register 2. - */ - uint32_t data_2:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_2_reg_t; - -/** Type of data_3 register - * Data register 3. - */ -typedef union { - struct { - /** data_3 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 3 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 3 and when - * software initiate read operation, it is rx data register 3. - */ - uint32_t data_3:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_3_reg_t; - -/** Type of data_4 register - * Data register 4. - */ -typedef union { - struct { - /** data_4 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 4 and when - * software initiate read operation, it is rx data register 4. - */ - uint32_t data_4:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_4_reg_t; - -/** Type of data_5 register - * Data register 5. - */ -typedef union { - struct { - /** data_5 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 5 and when - * software initiate read operation, it is rx data register 5. - */ - uint32_t data_5:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_5_reg_t; - -/** Type of data_6 register - * Data register 6. - */ -typedef union { - struct { - /** data_6 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 6 and when - * software initiate read operation, it is rx data register 6. - */ - uint32_t data_6:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_6_reg_t; - -/** Type of data_7 register - * Data register 7. - */ -typedef union { - struct { - /** data_7 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 7 and when - * software initiate read operation, it is rx data register 7. - */ - uint32_t data_7:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_7_reg_t; - -/** Type of data_8 register - * Data register 8. - */ -typedef union { - struct { - /** data_8 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 8 and when software initiate read operation, it - * is rx data register 8. - */ - uint32_t data_8:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_8_reg_t; - -/** Type of data_9 register - * Data register 9. - */ -typedef union { - struct { - /** data_9 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 9 and when software initiate read operation, it - * is rx data register 9. - */ - uint32_t data_9:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_9_reg_t; - -/** Type of data_10 register - * Data register 10. - */ -typedef union { - struct { - /** data_10 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 10 and when software initiate read operation, it - * is rx data register 10. - */ - uint32_t data_10:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_10_reg_t; - -/** Type of data_11 register - * Data register 11. - */ -typedef union { - struct { - /** data_11 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 11 and when software initiate read operation, it - * is rx data register 11. - */ - uint32_t data_11:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_11_reg_t; - -/** Type of data_12 register - * Data register 12. - */ -typedef union { - struct { - /** data_12 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 12 and when software initiate read operation, it - * is rx data register 12. - */ - uint32_t data_12:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_12_reg_t; - - -/** Group: Timestamp Register */ -/** Type of timestamp_data register - * Timestamp data register - */ -typedef union { - struct { - /** timestamp_data : RO; bitpos: [31:0]; default: 0; - * Data of timestamp of a CAN frame. - */ - uint32_t timestamp_data:32; - }; - uint32_t val; -} twai_timestamp_data_reg_t; - -/** Type of timestamp_prescaler register - * Timestamp configuration register - */ -typedef union { - struct { - /** ts_div_num : R/W; bitpos: [15:0]; default: 31; - * Configures the clock division number of timestamp counter. - */ - uint32_t ts_div_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} twai_timestamp_prescaler_reg_t; - -/** Type of timestamp_cfg register - * Timestamp configuration register - */ -typedef union { - struct { - /** ts_enable : R/W; bitpos: [0]; default: 0; - * enable the timestamp collection function. - */ - uint32_t ts_enable:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} twai_timestamp_cfg_reg_t; - - -typedef struct { - volatile twai_mode_reg_t mode; - volatile twai_cmd_reg_t cmd; - volatile twai_status_reg_t status; - volatile twai_interrupt_reg_t interrupt; - volatile twai_interrupt_enable_reg_t interrupt_enable; - uint32_t reserved_014; - volatile twai_bus_timing_0_reg_t bus_timing_0; - volatile twai_bus_timing_1_reg_t bus_timing_1; - uint32_t reserved_020[3]; - volatile twai_arb_lost_cap_reg_t arb_lost_cap; - volatile twai_err_code_cap_reg_t err_code_cap; - volatile twai_err_warning_limit_reg_t err_warning_limit; - volatile twai_rx_err_cnt_reg_t rx_err_cnt; - volatile twai_tx_err_cnt_reg_t tx_err_cnt; - volatile twai_data_0_reg_t data_0; - volatile twai_data_1_reg_t data_1; - volatile twai_data_2_reg_t data_2; - volatile twai_data_3_reg_t data_3; - volatile twai_data_4_reg_t data_4; - volatile twai_data_5_reg_t data_5; - volatile twai_data_6_reg_t data_6; - volatile twai_data_7_reg_t data_7; - volatile twai_data_8_reg_t data_8; - volatile twai_data_9_reg_t data_9; - volatile twai_data_10_reg_t data_10; - volatile twai_data_11_reg_t data_11; - volatile twai_data_12_reg_t data_12; - volatile twai_rx_message_counter_reg_t rx_message_counter; - uint32_t reserved_078; - volatile twai_clock_divider_reg_t clock_divider; - volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; - volatile twai_hw_cfg_reg_t hw_cfg; - volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; - volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; - volatile twai_eco_cfg_reg_t eco_cfg; - volatile twai_timestamp_data_reg_t timestamp_data; - volatile twai_timestamp_prescaler_reg_t timestamp_prescaler; - volatile twai_timestamp_cfg_reg_t timestamp_cfg; -} twai_dev_t; - -extern twai_dev_t TWAI0; -extern twai_dev_t TWAI1; -extern twai_dev_t TWAI2; - -#ifndef __cplusplus -_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif