Merge branch 'feature/c5_ulp' into 'master'

feat(ulp): add basic support for running lp core on C5

Closes IDF-8637

See merge request espressif/esp-idf!29496

components/hal/esp32c5/include/hal/lp_core_ll.h

@@ -0,0 +1,125 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use it in application code.
+ ******************************************************************************/
+
+#pragma once
+
+#include <stdbool.h>
+#include "soc/lpperi_struct.h"
+#include "soc/pmu_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU    BIT(0) // Started by HP core (1 single wakeup)
+#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART   BIT(1) // Enable wake-up by a certain number of LP UART RX pulses
+#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO     BIT(2) // Enable wake-up by LP IO interrupt
+#define LP_CORE_LL_WAKEUP_SOURCE_ETM       BIT(3) // Enable wake-up by ETM event
+#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER  BIT(4) // Enable wake-up by LP timer
+
+/**
+ * @brief Enable the bus clock for LP-coree
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void lp_core_ll_enable_bus_clock(bool enable)
+{
+    LPPERI.clk_en.lp_cpu_ck_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define lp_core_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the lp_core module
+ *
+ */
+static inline void lp_core_ll_reset_register(void)
+{
+    LPPERI.reset_en.lp_cpu_reset_en = 1;
+    LPPERI.reset_en.lp_cpu_reset_en = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define lp_core_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_reset_register(__VA_ARGS__)
+
+
+/**
+ * @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core
+ *
+ */
+static inline void lp_core_ll_hp_wake_lp(void)
+{
+    PMU.hp_lp_cpu_comm.hp_trigger_lp = 1;
+}
+
+/**
+ * @brief Enables the LP core debug module, allowing JTAG to connect
+ *
+ * @param enable enable if true, disable if false
+ */
+static inline void lp_core_ll_debug_module_enable(bool enable)
+{
+    LPPERI.cpu.lpcore_dbgm_unavaliable = !enable;
+}
+
+/**
+ * @brief Enables CPU reset at sleep
+ *
+ * @param enable enable if true, disable if false
+ */
+static inline void lp_core_ll_rst_at_sleep_enable(bool enable)
+{
+    PMU.lp_ext.pwr0.slp_reset_en = enable;
+}
+
+/**
+ * @brief Stall lp core cpu at sleep request
+ *
+ * @param enable enable if true, disable if false
+ */
+static inline void lp_core_ll_stall_at_sleep_request(bool enable)
+{
+    PMU.lp_ext.pwr0.slp_stall_en = enable;
+}
+
+/**
+ * @brief Set the wake-up source for the lp-core
+ *
+ * @param flags wake-up sources
+ */
+static inline void lp_core_ll_set_wakeup_source(uint32_t flags)
+{
+    PMU.lp_ext.pwr1.wakeup_en = flags;
+}
+
+/**
+ * @brief Get wake-up sources for the LP-core
+ */
+static inline uint32_t lp_core_ll_get_wakeup_source(void)
+{
+    return PMU.lp_ext.pwr1.wakeup_en;
+}
+
+/**
+ * @brief Request PMU to put LP core to sleep
+ */
+static inline void lp_core_ll_request_sleep(void)
+{
+    PMU.lp_ext.pwr1.sleep_req = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c5/include/hal/pmu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -671,6 +671,17 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
     return hw->clk_state0.sysclk_slp_sel;
 }
 
+
+FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
+{
+    return hw->lp_ext.int_raw.val;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
+{
+    hw->lp_ext.int_clr.val = mask;
+}
+
 #ifdef __cplusplus
 }
 #endif